JPS5785131A - Multiplexer channel - Google Patents
Multiplexer channelInfo
- Publication number
- JPS5785131A JPS5785131A JP16167180A JP16167180A JPS5785131A JP S5785131 A JPS5785131 A JP S5785131A JP 16167180 A JP16167180 A JP 16167180A JP 16167180 A JP16167180 A JP 16167180A JP S5785131 A JPS5785131 A JP S5785131A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- action
- register
- interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To greatly increase the processing speed, by ommitting an input/output connection action in case a device to be controlled of the input/output action coincidents with said device that carried out an input/output action immediately before. CONSTITUTION:When an interruption is accepted from an input/output device which is so far a device subject to an input/output action, an interruption acceptance approval signal is transmitted from an input/outut bus control circuit. Thus the contents of an interruption device number register is held in the 2nd register 402 of an address comparator 231 through a device number output line 230. On the other hand, the device number of an input/output device which was previously a subject of the input/output action is held in the 1st register 401. When thses two device numbers coincidents, an address coincidence signal is delivered to a decoding ROM215 from a comparator 403. Thus the ROM215 produces the head address of a microprogram for preparation of the data transfer. As a result, the connection is ommitted between a multiplexer channel and an input/output device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16167180A JPS5785131A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16167180A JPS5785131A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5785131A true JPS5785131A (en) | 1982-05-27 |
Family
ID=15739621
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16167180A Pending JPS5785131A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5785131A (en) |
-
1980
- 1980-11-17 JP JP16167180A patent/JPS5785131A/en active Pending
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