JPS5784150A - Large-scale integrated circuit device - Google Patents

Large-scale integrated circuit device

Info

Publication number
JPS5784150A
JPS5784150A JP16110380A JP16110380A JPS5784150A JP S5784150 A JPS5784150 A JP S5784150A JP 16110380 A JP16110380 A JP 16110380A JP 16110380 A JP16110380 A JP 16110380A JP S5784150 A JPS5784150 A JP S5784150A
Authority
JP
Japan
Prior art keywords
resistor
output buffer
buffer circuit
inside gate
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16110380A
Other languages
Japanese (ja)
Other versions
JPS6351380B2 (en
Inventor
Shuichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16110380A priority Critical patent/JPS5784150A/en
Publication of JPS5784150A publication Critical patent/JPS5784150A/en
Publication of JPS6351380B2 publication Critical patent/JPS6351380B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a master slice LSI enhancing driving ability of an inside gate to drive an output buffer circuit to load capacity and contriving to improve delay time by a method wherein a resistor is inserted between the input end of the output buffer circuit and an electric power source voltage. CONSTITUTION:The inside gate circuit A, the output buffer circuit B to constitute the gate array type master slice LSi are formed. Elements of transistor, resistor, etc., are formed previously in the master pattern forming region, and by changing the progress of wiring work, logic gates are formed and wirings between respective gates are performed. The LSI is formed as to insert the resistor R15 between the input end of the output buffer circuit B and the electric power source voltage VEE. A resistor R4 and the resistor R15 are connected in parallel to an emitter follower transistor Q5 of the inside gate to drive the output buffer circuit B to reduce resistance of the emitter follower, and driving force of the inside gate is increased.
JP16110380A 1980-11-14 1980-11-14 Large-scale integrated circuit device Granted JPS5784150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16110380A JPS5784150A (en) 1980-11-14 1980-11-14 Large-scale integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16110380A JPS5784150A (en) 1980-11-14 1980-11-14 Large-scale integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5784150A true JPS5784150A (en) 1982-05-26
JPS6351380B2 JPS6351380B2 (en) 1988-10-13

Family

ID=15728656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16110380A Granted JPS5784150A (en) 1980-11-14 1980-11-14 Large-scale integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5784150A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220948A (en) * 1983-05-31 1984-12-12 Toshiba Corp Semiconductor device
JPH01119051A (en) * 1987-10-30 1989-05-11 Nec Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220948A (en) * 1983-05-31 1984-12-12 Toshiba Corp Semiconductor device
JPH01119051A (en) * 1987-10-30 1989-05-11 Nec Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6351380B2 (en) 1988-10-13

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