JPH01119051A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce noise attributable to simultaneous operation of a plurality of circuits and to prevent erroneous operation of the circuits by relatively chang ing circuit constants of the output circuits which operate simultaneously, and finely adjusting the timing for their simultaneous operation. CONSTITUTION:By inserting a resistance, R6=0-100OMEGA, while changing its resis tance value to each of a plurality of output circuits which operate simultaneous ly, a delay in time constants DELTAt by R6 occurs in both outputs relative to the timing of the simultaneous operation, relatively reducing a component ndI/dt in equation (1). It is required in a diagram showing changes in output voltage and current that the sum of an ordinary delay DELTAt and R6 induced delay DELTAt be less than a delay required by circuit tpd, but DELTAt required for reducing dI/dt may be at levels of tr, tf, such being acceptable in terms of tpd required in ordinary simultaneous operations. Provided, L: self or mutual inductance compo nent of power or ground voltage: DELTAV: change in voltage by L; dI/dt: change in current by time per output circuit; n: number of simultaneous output operations.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and particularly to measures against noise caused by simultaneous operation of output circuits. The main source of noise is the output circuit that interfaces with the outside, and the noise generated in the output circuit affects internal circuits with small logic amplitudes, causing malfunctions. For this reason, conventional efforts have been made to separate the power supply system from the output system and wire the internal system in order to suppress noise to the internal system as much as possible.

On the other hand, noise in the output system is particularly large when there are multiple output circuits that operate simultaneously, and the noise generated by simultaneous operations causes malfunctions in other output circuits. Therefore, it is necessary to impose restrictions on the simultaneous operation of output circuits. FIG. 6 shows an example of measurement of noise caused by simultaneous operation of the output circuits. Figure 2 is an output circuit diagram of the integrated circuit used in the measurement.
istor-Transistor-Logic) circuit. CL is an external load. Figure 6 is the second
The figure shows the change in output potential over time when a plurality of TTL circuits are operated simultaneously. FIG. 6 also shows temporal changes in the power supply current and ground current. Output from Low to Hl
When changing to gh, the current in the circuit of FIG. 2a mainly passes through the path R4 to Q5 from the power supply to charge the external load C2. At this time, the power supply current fluctuates due to parasitic inductance components within the semiconductor and the package, and the resulting fluctuations in the power supply potential reduce the high-level noise margin of the output circuit connected to the common power supply. Fluctuations in the power supply current also cause fluctuations in the ground potential due to mutual inductance and the like, reducing the low-level noise margin of the output circuit or nearby internal circuits, which are unrelated to simultaneous operation. When the output changes from high level to low level, load C
Although current flows from L to Q4, the same phenomenon as described above causes circuit malfunction.

The potential fluctuation △V due to the self or mutual inductance component of the power supply or ground potential is determined by the time change in current per output circuit d I/d t and the number of simultaneous output operations n. It is expressed as (1). Increasing the speed of integrated circuits means reducing the time component dt,
High JT of bipolar transistors MO5) Improvements in performance such as gm by reducing the gate length of transistors mean an increase in the dl component, so the dI/dt component in equation (1) tends to become larger and larger. On the other hand, attempts are being made to reduce the inductance component by devising the layout of the power supply wiring and improving the package, but the current situation is that it is necessary to impose quite severe restrictions on the number of simultaneous operating outputs n.

For this reason, the number of power supply or ground terminals is often increased to stabilize the potential, but this often results in the inconvenience of a shortage of signal terminals.

[Differences between the Invention and the Prior Art] In contrast to the above-mentioned conventional noise countermeasures due to the simultaneous operation of output circuits, the present invention attempts to solve this problem from a circuit perspective.

[Means for Solving the Problems] The semiconductor integrated circuit of the present invention is characterized in that the circuit constants of each output circuit are changed in order to finely adjust the timing of output circuits that operate simultaneously.

Embodiment 1 FIG. 1(a) is a circuit diagram showing a first embodiment of the present invention. This is a TTL circuit similar to the example shown in FIG. 2, but it is characterized in that a resistor R6 is inserted in series with the base of the phase division stage transistor Q2. R for each output circuit that operates simultaneously
By using a resistor of 6=O to 100Ω with different resistance values, a time constant delay Δt due to R6 occurs between the outputs with respect to the timing of simultaneous operation, and n in equation (1) is relatively
The reduction in dI/dt component is measured. Figure 1(b) shows the temporal changes in the output potential and current. In Fig. 1(b), it is necessary that the sum of the normal delay t and the delay Δt due to R6 is less than the required delay tpd of the circuit, but dI/d
Δt required for relaxation of t may be about tr, tf,
There is a constant delay with respect to the tpd normally required for simultaneous operation.

In a second embodiment of the present invention, the dI/dt component is reduced by changing the resistors R1 and R2 between the simultaneously operated outputs in the circuit shown in FIG. Figure 3 shows the change in output potential over time. In Figure 3, A is the input potential from inside, B is the output potential of the circuit in Figure 2, and C is B
This shows the case where R1°R2 is increased. R
1 and R2 affect not only the delay of the output circuit but also the rise and fall times, and therefore have a further effect of reducing dl/dt. Although this has the opposite effect of limiting the operating frequency, it is highly effective in realizing a circuit that operates a large number of outputs simultaneously at a relatively low frequency.

In addition, 1. The resistance value in the second embodiment can be easily changed by changing the contact position of the P-type diffused resistor or polysilicon resistor.

A third embodiment in which the present invention is applied to a CMO5 circuit is shown in FIG. In the third embodiment, two stages of inverters are connected in series.
This is a MOS output circuit. MP1゜MP2 is P type, M
Nl and MN2 are N-type (7) MOS) transistors.

MP2. Since MN2 drives the external load CL, it is necessary to design the gate width to be very large. For this reason, MP2.
The gate capacitance of MN2 is very large, and it cannot be driven directly from the internal CMO5 circuit.
OS transistor and MP2. It is common to install a pre-buffer consisting of MPI and MNI having a gate width intermediate to that of MN2. In this embodiment, the gm (mutual conductance) of a MOS transistor used for the pre-buffer is varied between simultaneous operation outputs, and the output timing is changed to ease the number of simultaneous operations allowed.

Changing the gm of a MOS transistor is easily realized by changing the gate width.

Next, the application of the present invention to a gate array type integrated circuit will be described. In gate array type integrated circuits, a semiconductor substrate is prepared in advance with an underlayer process, and various circuits are realized through the overlay process. The second embodiment can be directly applied to the gate array method by changing the contact stroke blowdown to the top stroke.

When applying Embodiment 3, changing the gate width requires performing the selective oxidation process that defines the MOS region as the overlay process, and the overlay process is too long for the gate array method, which is characterized by short delivery times, making it impractical. do not have.

However, by taking advantage of the property that the gm of a MOS (MOS) transistor largely depends on the opening of the contacts in the source and drain regions, the output circuits operating simultaneously can be
By selectively using the contact opening methods shown in (b) and (c), the present invention can also be applied to gate array type integrated circuits.

[Effects of the Invention] As explained above, the present invention reduces the noise generated by simultaneous operations by mutually changing the circuit constants of a plurality of output circuits operating simultaneously and finely adjusting the timing of simultaneous operations. This has the effect of preventing circuit malfunction.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram of a TTL output circuit showing the first embodiment of the present invention, FIG. 1(b) is a time chart explaining its operation, and FIG. 2 is a circuit diagram of a conventional TTL circuit. , 3rd
The figure is a time chart diagram showing the operation of the second embodiment when the present invention is applied to the circuit of Figure 2. Figure 4 is a circuit diagram of the CMO3 output circuit which is the third application target of the present invention. Figures 5 (a), (b), and (c) are plan views of MOS transistors for explaining the method of concretely realizing the present invention when the present invention is applied to a CMOS gate array, and Figure 6 is a plan view of a MOS transistor when the present invention is applied to a CMOS gate array. It is a graph showing an example of measuring noise during operation. R1~R6Φ・φ・Φ・Resistance, Q1~Q4...NPN with Schottky clamp)
Ransistor, Q5...◆...NPN) Ransistor, CL...
......External load, MPI, MP2...P type MO9) transistor, MN
I, MN2 competition...N type MO5) transistor. Patent Applicant: NEC Corporation Agent, Patent Attorney Kiyoshi Kuwai - Figure 1 (a) Figure 2 Figure 4 Figure 5 Colo Diagram

Claims (2)

[Claims] (1) A semiconductor integrated circuit in which a plurality of output circuits on the same substrate are operated simultaneously, and the timing of simultaneous operation is finely adjusted by changing the circuit constant of each output circuit. (2) The semiconductor integrated circuit is of a gate array type, in which circuit elements for simultaneous operation timing adjustment are prepared in advance in the underlay process, and the circuit elements are selectively used in the overlay process depending on the circuit. The semiconductor integrated circuit described.