KR100587027B1 - Error prevention circuit for dram merged logic circuit - Google Patents

Abstract

The present invention relates to a malfunction prevention circuit of a DRAM embedded logic circuit, and in the related art, every overshoot or under is performed through a capacitor (terminal ⓒ, ⓓ) formed between a deep N-Well and a substrate. There was a problem that the parasitic current flowed in each chute, causing the back bias potential of -2 volts to change, causing the chip to malfunction. Therefore, in the present invention, the overshoot and undershoot generated when the input signal is changed by the damping resistor R1 is reduced, and the ground power is applied to the substrate by stably placing the deep n well in the DRAM portion, thereby stably maintaining the substrate. It is effective.

Description

ERROR PREVENTION CIRCUIT FOR DRAM MERGED LOGIC CIRCUIT}

1 is a cross-sectional view of a logic circuit incorporating a conventional DRAM.

2 is a conventional input protection circuit diagram.

3 is an exemplary diagram of an input waveform including overshoot and undershoot.

4 is an input protection circuit diagram of a DRAM embedded logic circuit according to the present invention;

5 is a cross-sectional view of a logic circuit incorporating a DRAM according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

D1, D2: Diode NM1: Internal Morse Transistor

R1: resistance

The present invention relates to a malfunction prevention circuit of a built-in DRAM circuit, and particularly to prevent malfunction caused by noise such as overshoot and undershoot of an input terminal in a chip including DRAM in a circuit composed of pure logic only. The present invention relates to a malfunction prevention circuit of a DRAM built-in logic circuit.

1 is a cross-sectional view of a logic circuit in which a conventional DRAM is embedded, and as shown therein, a region P + formed in a DRAM region on a P-substrate and connected to a back bias voltage generator; Deep N-Well formed in the electrostatic discharge (ESD) region on the substrate; An N-Well and a P-Well formed adjacent to each other by an isolation N-Well on the deep N-well; An N region N + formed on the isolation N-Well and connected to a power supply voltage VDD and a gate electrode; An N region formed on the N-Well and connected to the power supply voltage VDD and the gate electrode, and formed adjacent to the N region N + and connected to the power supply voltage VDD and the gate electrode. An area P + connected to the input pad PAD and spaced apart from the area P + by a predetermined distance; The N region N + formed on the P-Well and connected to the input pad and the N region N + connected to the ground VSS and the gate electrode at a predetermined distance from the N region N + and the N region It is formed in close proximity to (N +) and is composed of a ground region (P +) connected to the ground (VSS) and the gate electrode.

In addition, the structure of the input protection circuit for preventing electrostatic discharge (ESD) at this time is the diode (D1, D2) between the power supply voltage (VDD) and ground (GND) as shown in FIG. Is connected in series and configured to apply an input waveform to the gate of the internal MOS transistor NM1 through its common connection point.

Hereinafter, the operation and operation of the conventional DRAM embedded logic circuit configured as described above will be described.

First, the input waveform is input into the chip through the input pad PAD in FIG.

At this time, if a normal square wave signal is input, there is no problem, but a signal waveform of a noise component having an overshoot or undershoot is input on an actual board as shown in the waveform diagram of FIG. 3.

At this time, a forward diode is formed between an N-Well and a Deep N-Well of the same type as the region P + serving as the input protection circuit of FIG. It flows into the substrate (P-Substrate).

As described above, in the related art, parasitic current flows and is maintained at every overshoot or undershoot through the capacitors (terminals ⓒ and ⓓ) formed between the Deep N-Well and the substrate. There was a problem of causing chip malfunction by changing the back bias potential of -2 volts.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and by modifying the input protection circuit to control the occurrence of overshoot below the turn-on voltage (Vd) of the diode, the DRAM built-in logic circuit for preventing malfunction The purpose is to provide a malfunction prevention circuit.

According to the present invention for achieving the above object, the diode (D1, D2) is connected in series between the power supply voltage (VDD) and the ground (GND), the signal waveform input through the resistor (R1) at its common connection point This is achieved by configuring the gate of the internal MOS transistor NM1, which will be described in detail with reference to the accompanying drawings.

4 is an input protection circuit diagram of a DRAM embedded logic circuit according to an embodiment of the present invention, in which diodes D1 and D2 are connected in series between a power supply voltage VDD and a ground GND, and at a common connection point thereof. The signal waveform input through the resistor R1 is configured to be applied to the gate of the internal MOS transistor NM1.

5 is a cross-sectional view of a logic circuit incorporating a DRAM according to the present invention, in which a position of a deep N-Well on a P-substrate is placed on a DRAM portion of the logic circuit instead of an electrostatic discharge portion. The operation and action of the present invention configured as described above are described.

First, in FIG. 4, overshoot and undershoot generated when the input signal is changed by the damping resistor R1 are reduced.

If the overshoot and undershoot are kept below 0.6 volts, which is the diode turn-on voltage, there is no parasitic current flow in the chip, and the substrate maintains a constant back bias of -2 volts.

In this case, the chip defect caused by inserting about 100 으로 는 into the damping resistor R1 may be considered to reduce the DC current and the timing delay, but it is a very small value and does not affect the overall chip operation.

Meanwhile, as shown in FIG. 5, the deep N-Well is positioned in the DRAM portion instead of the electrostatic discharge unit so that ground (VSS) power is applied to the substrate, thereby providing a substrate having fundamental stability. Even if a conventional input protection circuit other than the modified input protection circuit such as is used, no problem occurs.

As described above, in the malfunction prevention circuit of the DRAM embedded logic circuit of the present invention, the overshoot and undershoot generated when the input signal is changed by the damping resistor R1 is reduced, and the deep nwell is placed on the DRAM part. The ground power is applied to the substrate to stabilize the substrate.

Claims (2)

delete In a logic circuit in which a DRAM and an electrostatic discharge unit are integrated, a ground (VSS) power source is applied to a substrate by placing a Deep N-Well in a DRAM part on a P-type substrate. Malfunction prevention circuit of DRAM built-in logic circuit.

Images