JPS57124942A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS57124942A
JPS57124942A JP999481A JP999481A JPS57124942A JP S57124942 A JPS57124942 A JP S57124942A JP 999481 A JP999481 A JP 999481A JP 999481 A JP999481 A JP 999481A JP S57124942 A JPS57124942 A JP S57124942A
Authority
JP
Japan
Prior art keywords
level
output
input signal
misfets
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP999481A
Other languages
Japanese (ja)
Inventor
Yasuo Akatsuka
Toru Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP999481A priority Critical patent/JPS57124942A/en
Publication of JPS57124942A publication Critical patent/JPS57124942A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the number of transistors (TRs) and to accelerate the switching speed, by connecting each two MISFETs in series between the 1st power supply and the 1st node and between the 1st node and the 2nd power supply, and inputting an input signal or an auxiliary signal to each gate. CONSTITUTION:When input signals A, B are both at L level, TRs Q1, Q4, Q7, Q8 turn on out of 8 MISFETs, other TRs Q2, Q3, Q5, Q6 turn off, and only a path from an output X to GND via the MISFETs Q5, Q6 is conductive, and the output X is at L level. When the input signal A is at L level, the input signal B is at H level, or when the input signal A is at H level and the input signal B is at L level, only a path from the power supply Vcc to the output X via FETs Q1, Q2 or Q3, Q4 is conductive and the output X is at H level. When the input signals A, B are both at H level, only a path from the output X to GND via the FETs Q5, Q6 is conductive and the output X is at L level.
JP999481A 1981-01-26 1981-01-26 Logical circuit Pending JPS57124942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP999481A JPS57124942A (en) 1981-01-26 1981-01-26 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP999481A JPS57124942A (en) 1981-01-26 1981-01-26 Logical circuit

Publications (1)

Publication Number Publication Date
JPS57124942A true JPS57124942A (en) 1982-08-04

Family

ID=11735405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP999481A Pending JPS57124942A (en) 1981-01-26 1981-01-26 Logical circuit

Country Status (1)

Country Link
JP (1) JPS57124942A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570597A1 (en) * 1991-12-09 1993-11-24 Fujitsu Limited Flash memory improved in erasing characteristic, and circuit therefor
US5483216A (en) * 1992-05-21 1996-01-09 Ubukata Industries Co, Ltd. Fixing assembly of a temperature responsive element and its fixing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4953757A (en) * 1972-09-28 1974-05-24
JPS49126249A (en) * 1973-04-04 1974-12-03

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4953757A (en) * 1972-09-28 1974-05-24
JPS49126249A (en) * 1973-04-04 1974-12-03

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570597A1 (en) * 1991-12-09 1993-11-24 Fujitsu Limited Flash memory improved in erasing characteristic, and circuit therefor
EP0570597A4 (en) * 1991-12-09 1998-11-11 Fujitsu Ltd Flash memory improved in erasing characteristic, and circuit therefor
EP0954102A1 (en) * 1991-12-09 1999-11-03 Fujitsu Limited Exclusive or/nor circuits
US5483216A (en) * 1992-05-21 1996-01-09 Ubukata Industries Co, Ltd. Fixing assembly of a temperature responsive element and its fixing method

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