JPS648715A - Logic circuit device - Google Patents

Logic circuit device

Info

Publication number
JPS648715A
JPS648715A JP62165048A JP16504887A JPS648715A JP S648715 A JPS648715 A JP S648715A JP 62165048 A JP62165048 A JP 62165048A JP 16504887 A JP16504887 A JP 16504887A JP S648715 A JPS648715 A JP S648715A
Authority
JP
Japan
Prior art keywords
trs
logic circuit
gate
input
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165048A
Other languages
Japanese (ja)
Inventor
Eiji Ikuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62165048A priority Critical patent/JPS648715A/en
Publication of JPS648715A publication Critical patent/JPS648715A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the operating speed by turning on 2nd, 3rd and 6th switching elements when 1st and 2nd control signals are both at a 1st logic level and turning off 1st and 5th switching elements thereby constituting the logic circuit device by a few switch number. CONSTITUTION:The logic circuit device is formed by a JK-FF and consists of four transfer gates 1-4, 2 level fixing transistors(TRs) N5, P5, 5 inverters 11-15 and a D-FF(DF). The gates 1, 2 are constituted by P and N-channel MOS TRs P1, N1 and TRs P2, N2, and gates 3, 4 are constituted by P and N-channel MOS TRs P3, N3, and TRs P4, N4 similarly. An inverting output signal, inverse of Q is input to the input terminal of the gate 1 from the FFDF and fed to the gate 3 via an inverter 13. Moreover, the output signal Q of the FFDF is input to the input terminal of the gate 2 and its output is input to the gate 4 via an inverter 14. Then the logic circuit decides the two output stages by a few switch numbers.
JP62165048A 1987-06-30 1987-06-30 Logic circuit device Pending JPS648715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165048A JPS648715A (en) 1987-06-30 1987-06-30 Logic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165048A JPS648715A (en) 1987-06-30 1987-06-30 Logic circuit device

Publications (1)

Publication Number Publication Date
JPS648715A true JPS648715A (en) 1989-01-12

Family

ID=15804845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165048A Pending JPS648715A (en) 1987-06-30 1987-06-30 Logic circuit device

Country Status (1)

Country Link
JP (1) JPS648715A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196213A (en) * 1990-03-29 1993-03-23 Fanuc Ltd. Ejector mechanism in an injection molding machine
US5310331A (en) * 1990-06-16 1994-05-10 Fanuc Ltd Injection molding machine with a mold core drive apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196213A (en) * 1990-03-29 1993-03-23 Fanuc Ltd. Ejector mechanism in an injection molding machine
US5310331A (en) * 1990-06-16 1994-05-10 Fanuc Ltd Injection molding machine with a mold core drive apparatus

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