JPS6450620A - Semiconductor logic element - Google Patents
Semiconductor logic elementInfo
- Publication number
- JPS6450620A JPS6450620A JP62206417A JP20641787A JPS6450620A JP S6450620 A JPS6450620 A JP S6450620A JP 62206417 A JP62206417 A JP 62206417A JP 20641787 A JP20641787 A JP 20641787A JP S6450620 A JPS6450620 A JP S6450620A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input
- polycrystal silicon
- logic element
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To attain forming of a logic element to a multi-stage input by forming the logic to plural input stages by one transistor(TR) and a resistor. CONSTITUTION:For example, a TR is a N-channel MOSFET 5. A resistor 4 formed by doping phosphor to a polycrystal silicon by a desired quantity is connected to three input sections 1, 2, 3 respectively. The resistors 4 are connected in common to a gate section 6 of the MOSFET 5. The source 7 of the MOSFET is connected to ground and the drain 8 is connected to a resistor 9 made of a polycrystal silicon and the output 10. Moreover, the other end of the polycrystal silicon 9 is connected to an external power supply 11. Furthermore, the resistor 9 made of polycrystal silicon is formed at the same time as the resistor 4 and its resistance is set independently of the resistor 4. Thus, the output to the 3-input gate is set independently of each input and a logic element is formed by using one TR.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62206417A JPS6450620A (en) | 1987-08-21 | 1987-08-21 | Semiconductor logic element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62206417A JPS6450620A (en) | 1987-08-21 | 1987-08-21 | Semiconductor logic element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6450620A true JPS6450620A (en) | 1989-02-27 |
Family
ID=16523025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62206417A Pending JPS6450620A (en) | 1987-08-21 | 1987-08-21 | Semiconductor logic element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6450620A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0665125U (en) * | 1993-02-26 | 1994-09-13 | 広育 伊倉 | Snowfall prevention structure for automobiles |
KR100704350B1 (en) * | 2002-11-13 | 2007-04-06 | 다 탕 모바일 커뮤니케이션즈 이큅먼트 코포레이션 리미티드 | Method for multi-user demodulation with variable spread spectrum coefficient |
EP1777130A1 (en) | 1999-05-25 | 2007-04-25 | Toshio Murakami | Method and device for wiping |
-
1987
- 1987-08-21 JP JP62206417A patent/JPS6450620A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0665125U (en) * | 1993-02-26 | 1994-09-13 | 広育 伊倉 | Snowfall prevention structure for automobiles |
EP1777130A1 (en) | 1999-05-25 | 2007-04-25 | Toshio Murakami | Method and device for wiping |
KR100704350B1 (en) * | 2002-11-13 | 2007-04-06 | 다 탕 모바일 커뮤니케이션즈 이큅먼트 코포레이션 리미티드 | Method for multi-user demodulation with variable spread spectrum coefficient |
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