GB1135059A - Method of making semiconductor devices - Google Patents

Method of making semiconductor devices

Info

Publication number
GB1135059A
GB1135059A GB5412465A GB5412465A GB1135059A GB 1135059 A GB1135059 A GB 1135059A GB 5412465 A GB5412465 A GB 5412465A GB 5412465 A GB5412465 A GB 5412465A GB 1135059 A GB1135059 A GB 1135059A
Authority
GB
United Kingdom
Prior art keywords
output
input
semiconductor devices
inverter
dec
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5412465A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of GB1135059A publication Critical patent/GB1135059A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

1,135,059. Semi-conductor circuits. TEXAS INSTRUMENTS Inc. 21 Dec., 1965 [21 Dec., 1964], No. 54124/65. Heading H3T. [Also in Division H1] The invention relates to the construction of an integrated circuit (see Division H1) in which a basic circuit element may consist of a logic circuit as shown in Fig. 2. This comprises two AND gates 27, 28 with emitter follower output transistors 36, 37 (Fig. 3) and input terminals A and G and B and G respectively. The output across common load resistor 40 is connected via an inverter 43 to one input of AND gate 29 which has a second input terminal X, the output being supplied via emitter follower 47 to inverter 31 to provide the output/input G.
GB5412465A 1964-12-21 1965-12-21 Method of making semiconductor devices Expired GB1135059A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42003164A 1964-12-21 1964-12-21

Publications (1)

Publication Number Publication Date
GB1135059A true GB1135059A (en) 1968-11-27

Family

ID=23664787

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5412465A Expired GB1135059A (en) 1964-12-21 1965-12-21 Method of making semiconductor devices

Country Status (10)

Country Link
JP (1) JPS5011235B1 (en)
BE (1) BE674126A (en)
CH (1) CH475652A (en)
DE (1) DE1514910A1 (en)
DK (1) DK118474B (en)
ES (1) ES320796A1 (en)
FR (1) FR1460406A (en)
GB (1) GB1135059A (en)
NL (1) NL6516643A (en)
SE (2) SE315338B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
JPS54100349U (en) * 1977-12-27 1979-07-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

Also Published As

Publication number Publication date
SE315338B (en) 1969-09-29
ES320796A1 (en) 1966-05-16
SE346420B (en) 1972-07-03
BE674126A (en) 1966-04-15
CH475652A (en) 1969-07-15
NL6516643A (en) 1966-06-22
DK118474B (en) 1970-08-24
DE1514910A1 (en) 1970-11-26
FR1460406A (en) 1966-11-25
JPS5011235B1 (en) 1975-04-28

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