GB1252795A - - Google Patents

Abstract

1,252,795. Transistor logic circuits. NIPPON TELEGRAPH & TELEPHONE PUBLIC CORP. 21 May, 1969 [22 May, 1968], No. 25932/69. Heading H3T. A logic circuit is made up of a plurality of inverter type circuits comprising a transistor 6 having collector and emitter resistors 8, 9 connecting it between the supply terminals 1, 2, R8 being greater than R9 and the supply voltage being less than twice the base-emitter voltage drop V BE of the transistor. This swing preferably equals the value of V BE . less the collector to emitter saturation voltage V CE . The transistor thus operates over a linear range from a fully-on but nevertheless not saturated condition, to the just-off condition where the base voltage is just below V BE . Consequently fast operation is obtained, and the low voltages and low values of R8, R9 produce low power consumption. Two transistors 6, 7 in parallel act as an OR gate, and the voltage swing at the collector is at the correct level to apply directly to the base of a succeeding stage 3, 4. Lower level logic signals may be used by applying the input to an intermediate point (between 9, 10, Fig. 6, not shown), in the emitter resistor and taking the output from an emitter follower (12). In another embodiment, the logic circuit includes a transistor wherein the signal is applied only to the emitter circuit the base being connected to the positive supply (Fig. 7, not shown) or connected to an intermediate point in the collector resistor (between 8, 14, Fig. 8, not shown). Alternatively the base bias may come from a resistor-dioderesistor chain across the supply (Fig. 9, not shown). Each inverter circuit of the logic circuit of the invention may be incorporated in a Schmitt circuit (Fig. 10, not shown) or in an emitter coupled type circuit (Figs. 11, 13,14, not shown). An AND gate may be incorporated in the logic circuit of the invention using opposite conductivity type transistors (26, 27, Fig. 15, not shown). Two bi-stable circuits (Figs. 16, 17, not shown) embody the inverter circuits, one having two pairs (6, 7, 19, 31) of transistors one pair crosscoupled with the other and the inputs being received at those bases not cross connected; and the other having two cross-coupled transistors (7, 19) receiving the inputs in their emitter circuits. Voltage regulating circuits for the logic circuits (Figs. 18, 19, 20, not shown) are described.