JPS5782268A - Virtual storage control system - Google Patents
Virtual storage control systemInfo
- Publication number
- JPS5782268A JPS5782268A JP55158313A JP15831380A JPS5782268A JP S5782268 A JPS5782268 A JP S5782268A JP 55158313 A JP55158313 A JP 55158313A JP 15831380 A JP15831380 A JP 15831380A JP S5782268 A JPS5782268 A JP S5782268A
- Authority
- JP
- Japan
- Prior art keywords
- address
- conversion
- register
- bit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To convert a logical address into an arbitrary real address by providing a conversion table between a conversion code designating an address space and a part of real address. CONSTITUTION:A virtual storage system being an address extension circuit of a microprocessor 1 consists of a register 4 having a code designating the address space and a conversion circuit 6 forming the upper rank bit of the extended address from the conversion code formed with the content of the upper rank 4-bit of the logical address of an address bus 2. A switching circuit 16 selects the data taking a part of the extended address as 0 from a register 13 when the conversion circuit 6 is impossible, and the real address of a main memory 9 is formed to a register 8. When the address conversion is made at the conversion circuit 6, the converted address constitutes the upper rank 8-bit of the extended address.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55158313A JPS6034139B2 (en) | 1980-11-12 | 1980-11-12 | virtual storage controller |
KR1019810002843A KR860000792B1 (en) | 1980-11-12 | 1981-08-05 | Virtual memory control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55158313A JPS6034139B2 (en) | 1980-11-12 | 1980-11-12 | virtual storage controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5782268A true JPS5782268A (en) | 1982-05-22 |
JPS6034139B2 JPS6034139B2 (en) | 1985-08-07 |
Family
ID=15668895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55158313A Expired JPS6034139B2 (en) | 1980-11-12 | 1980-11-12 | virtual storage controller |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6034139B2 (en) |
KR (1) | KR860000792B1 (en) |
-
1980
- 1980-11-12 JP JP55158313A patent/JPS6034139B2/en not_active Expired
-
1981
- 1981-08-05 KR KR1019810002843A patent/KR860000792B1/en active
Also Published As
Publication number | Publication date |
---|---|
KR830006763A (en) | 1983-10-06 |
KR860000792B1 (en) | 1986-06-25 |
JPS6034139B2 (en) | 1985-08-07 |
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