KR830006763A - Virtual memory control method - Google Patents
Virtual memory control method Download PDFInfo
- Publication number
- KR830006763A KR830006763A KR1019810002843A KR810002843A KR830006763A KR 830006763 A KR830006763 A KR 830006763A KR 1019810002843 A KR1019810002843 A KR 1019810002843A KR 810002843 A KR810002843 A KR 810002843A KR 830006763 A KR830006763 A KR 830006763A
- Authority
- KR
- South Korea
- Prior art keywords
- address
- conversion
- address space
- main memory
- processing program
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims 4
- 238000006243 chemical reaction Methods 0.000 claims description 29
- 235000009852 Cucurbita pepo Nutrition 0.000 claims 1
- 241000219104 Cucurbitaceae Species 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 복수의 어드레스공간을 갖는 메모리의 어드레싱의 일례를 나타낸 도면.1 shows an example of addressing of a memory having a plurality of address spaces.
제2도는 복수의 어드레스공간에 있어서의 프로그램의 논리어드레스 할당도.2 is a logical address allocation diagram of a program in a plurality of address spaces.
제3도는 본원 발명의 일실시예를 나타낸 어드레스확장회로의 블록도.3 is a block diagram of an address expansion circuit showing an embodiment of the present invention.
제4도는 본원 발명의 일실시예에 있어서의 어드레스변환회로의 내부 변환테이블의 일례를 나타낸 도면.4 is a diagram showing an example of an internal conversion table of the address conversion circuit in one embodiment of the present invention.
제5도는 복수의 어드레스공간에 있어서의 프로그램의 실어드레스 할당도.5 is a real address allocation diagram of a program in a plurality of address spaces.
제6도는 본원 발명의 다른 실시예를 나타낸 어드레스확장회로의 블록도.6 is a block diagram of an address expansion circuit showing another embodiment of the present invention.
제7도는 다른 실시예에 있어서의 변환용 메모리 내용의 일례를 나타낸 도면.FIG. 7 is a diagram showing an example of the contents of a conversion memory in another embodiment. FIG.
Claims (3)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55158313A JPS6034139B2 (en) | 1980-11-12 | 1980-11-12 | virtual storage controller |
JP80-158313 | 1980-11-12 | ||
JP158313 | 1980-11-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR830006763A true KR830006763A (en) | 1983-10-06 |
KR860000792B1 KR860000792B1 (en) | 1986-06-25 |
Family
ID=15668895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019810002843A KR860000792B1 (en) | 1980-11-12 | 1981-08-05 | Virtual memory control method |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6034139B2 (en) |
KR (1) | KR860000792B1 (en) |
-
1980
- 1980-11-12 JP JP55158313A patent/JPS6034139B2/en not_active Expired
-
1981
- 1981-08-05 KR KR1019810002843A patent/KR860000792B1/en active
Also Published As
Publication number | Publication date |
---|---|
JPS5782268A (en) | 1982-05-22 |
KR860000792B1 (en) | 1986-06-25 |
JPS6034139B2 (en) | 1985-08-07 |
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