JPH0517583B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an address conversion device that converts a logical address in a logical address space to a physical address in a main storage device. [Technical background of the invention and its problems] In order to execute a program, the program must be allocated to a certain area of the main storage device. How multiple programs are allocated to main memory has a great impact on the efficiency of the entire system. In the real storage system, multiple programs are allocated to consecutive areas on the main storage device. In contrast, virtual memory systems separate the address space (virtual address space) of each program from the address space (real address space) on the main memory, and map the virtual address space to the real address space during execution. This method is often used in recent computer systems because it does not have the same limitations as the real storage method. There are two types of virtual storage systems: segment type and paging type. The segment method is a method in which a logical group of programs and data is treated as a segment, and a logical address is constructed by a segment number and an address within the segment. The paging method divides the main memory into fixed point areas called pages, and uses a virtual memory to perform mapping between pages in the logical address space and pages in the real address space on the main memory. In the segment method, since segments are continuous in the main memory, the user can create a program with segmentation in mind. However, if a segment becomes unnecessary and you try to allocate another segment to the main memory, if the segment to be allocated is too long, it will not be possible to store it in the unnecessary part, leaving a useless part on the main memory. arise. In consideration of such circumstances, a segment paging method, which is a combination of a segment method and a paging method, has been adopted in recent years. This segment
The paging method is shown in FIG. This method first treats a logical group of programs, data, etc. as a segment, and treats the addresses within this segment as logical addresses. This segment is allocated in the same way as the segment method, but in this segment paging method it is allocated in a virtual linear address space. The virtual linear address space is a virtual address space and is not limited by the size of the main storage device. This virtual linear address space is then paged and mapped with the real address space of the main storage device. For example, consider a program consisting of 3400 bytes as shown in Figure 3a. The logical addresses of this program 21 start from address 0000 and end at address 33FF. Program 21 0000-07FF
The address is 1st page 211, 0800-17FF address is 2nd page 212, 1800-27FF address is 3rd page
213, and addresses 2800 to 33FF are the fourth page 214. This program 21 sets the segment base address to 1800 and the area 22 of the virtual linear address space.
assigned to. The linear addresses of the program 22 are addresses 1800 to 4BFF. Program 22
The first page is 221, and the second, third, and fourth pages are 222, 223, and 224. Next, this virtual linear address space is subjected to paging processing and allocated to a vacant page on the main storage device. That is, program area 2 of the main memory
4, the first page of program 22 from 4800
Store at address 4FFF (241) and set the second page to 2000.
～Stored at address 2FFF (242) and the third page
The fourth page is stored at addresses 6000 to 6FFF (243), and the fourth page is stored at addresses 1000 to 1BFF (244). Since the virtual linear address space and the physical address space are mapped in this way, the associative memory showing the mapping of these spaces is as shown in Table 1 below.

[Purpose of the invention]

A first object of the present invention is to provide an address translation device that can perform translation from a logical address to a physical address at high speed. A second object of the present invention is to provide an address translation device capable of translating a logical address into a physical address using a small-scale circuit. [Summary of the Invention] The present invention provides an address conversion device that converts a logical address in a logical address space into a physical address of a main storage device, which includes a logical address register that stores the logical address, and a logical address register that is allocated to a virtual linear address space. A segment base register that stores a segment base address that is the start address of a segment, an in-page address of the logical address stored in the logical address register, and an in-page address of the segment base address stored in the segment base register. an addition means for adding together to generate an in-page address of the physical address; and a page address of the physical address based on the page address of the physical address, the page address of the segment base address, and a carry output of the addition means. The present invention is characterized in that it comprises an associative memory means for generating , a page address generated from the associative memory means, and a physical address register for storing an intra-page address generated from the addition means. [Embodiment of the Invention] FIG. 1 shows an address translation device according to a first embodiment of the invention. A 32-bit logical address to be converted is stored in the logical address register 12.
The segment base register 11 contains the starting address of the segment in the virtual linear address space.
A 32-bit segment base address is stored. The lower 12 bits indicating the intra-page address of the segment base register 11 and the lower 12 bits indicating the intra-page address of the logical address register 12 are input to each port of the adder 13. The upper 20 bits indicating the page address of the segment base register 11 and the upper 20 bits indicating the page address of the logical address register 12 are the content addressable memory 1.
5 is input. Further, the carry output of the adder 13 is input to the associative memory 15. Third
In the case of segmentation and paging as shown in the figure, the contents of the associative memory 15 are set as shown in Table 2 below.

[Table] The output of the associative memory 15 is stored in the upper 20 bits of the physical address register 16. The lower 12 bits of the physical address register 16 contain the 12 bits of the adder 13.
The bit addition result is input. Next, the operation of this embodiment will be explained by taking as an example the case where segmentation and paging are as shown in FIG. The segment base address of program 21 allocated to the virtual linear address space is
Since it is 1800 in hexadecimal notation, a segment base address of "1800" (in hexadecimal notation) is set in the segment base register 11 in advance. Now 0
Consider the case of converting the logical address of an address. In this case, data “0” (in hexadecimal notation) indicating the 0th logical address is first stored in the logical address register 12.
Set. Then, the adder 13 inputs "800" (hexadecimal representation), which is the lower 12 bits of the segment base register 11 (the in-page address of the segment base address), and the lower bits of the logical address register 12 (the in-page address of the logical address). Add “0” (hexadecimal representation),
The sum “800” is the lower 12 bits of the physical address register 16 (address within the page of the physical address).
Set to . At this time, since no carry occurs in the above addition, the adder 13 outputs a carry output "0" to the associative memory 15. The associative memory 15 contains the upper 20 bits of the segment base register 11 (page address of the segment base address).
Since "1" (hexadecimal representation) is input, and "0" (hexadecimal representation) is the upper 20 bits of the logical address register 12 (page address of the physical address), "4" is input based on Table 2. ” is output,
It is set in the upper 20 bits of the physical address register 16 (page address of the physical address). As a result, “4800” is stored in the physical address register 16.
(in hexadecimal notation) is set, and the physical address of address 4800 is output. Next, the case of converting the logical address of address 2FFF will be explained. Set "2FFF" (in hexadecimal notation) indicating the 2FFF address of the logical address in the logical address register 12. Then, the adder 13 inputs “800” (hexadecimal representation), which is the lower 12 bits of the segment base register 11, and the logical address register 1.
Add “FFF” which is the lower 12 bits of 2,
Set the lower 12 bits of the physical address register 16 to “7FF”. At this time, since a carry occurs in the above addition, the adder 13 outputs a carry output "1" to the associative memory 15. The associative memory 15 contains the upper 20 bits of the segment base register 11, which is “1” (in hexadecimal notation), and the upper 20 bits of the logical address register 12, which is “2”.
(in hexadecimal) is input, so "1" is output based on Table 2, and physical address register 1
It is set to the upper 20 bits of 6. As a result, "17FF" is set in the physical address register 16, and the physical address of address 17FF is output. In this way, the logical address of the program 21 shown in FIG. 3 can be converted into a physical address. Also, while the conventional example required a 32-bit adder 3, this embodiment requires only a 12-bit adder, and this embodiment can perform address conversion at high speed with a smaller circuit. . Furthermore, in the conventional example, the adder 3 performs segment processing and the associative memory 5 performs paging processing sequentially, whereas in this embodiment, the arithmetic operation of the adder 13 and the associative memory Since 15 operations are performed in parallel, segment processing and paging processing can be performed in parallel, and address conversion can be performed at high speed. As a result, according to this embodiment, address conversion can be performed at high speed with a small-scale circuit. An address translation device according to a second embodiment of the present invention is shown in FIG. In this embodiment, the upper 20 bits of the segment base register 11 and the upper 20 bits of the logical address register 12 are input to the associative memory 15, and the first and second page addresses are output.
These first and second page addresses are input to the selection circuit 18. The selection circuit 18 is the adder 13
The above first and second
, and outputs it to the physical address register 16. In the associative memory 15 of this embodiment, segmentation and paging are
In the case shown in the figure, the settings are as follows.

〔Effect of the invention〕

As described above, according to the present invention, a logical address can be converted into a physical address at high speed with a small-scale circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address translation device according to a first embodiment of the present invention, FIG. 2 is a block diagram of an address translation device according to a second embodiment of the present invention, and FIG. 3 is an explanation showing a segment paging method. figure,
FIG. 4 is a block diagram of a conventional address translation device. 1, 11...Segment base register, 2, 1
2...Logical address register, 3,13...Adder,
5, 15... associative memory, 6, 16... physical address register, 18... selection circuit.

Claims (1)

[Claims] 1. An address conversion device that converts a logical address in a logical address space into a physical address in a main storage device, comprising: a logical address register that stores the logical address; and a segment allocated to the virtual linear address space. Add the segment base register that stores the segment base address that is the start address, the in-page address of the logical address stored in the logical address register, and the in-page address of the segment base address stored in the segment base register. adding means for generating an in-page address of the physical address based on the page address of the logical address, the page address of the segment base address, and a carry output of the adding means; 1. An address translation device comprising: an associative memory means for storing a page address generated from the associative memory means; and a physical address register storing an intra-page address generated from the adding means. 2. In an address conversion device that converts a logical address in a logical address space to a physical address in a main storage device, the logical address register stores the logical address, and the segment base is the starting address of the segment allocated to the virtual linear address space. A segment base register that stores an address; and a page of the physical address by adding the in-page address of the logical address stored in the logical address register and the in-page address of the segment base address stored in the segment base register. an addition means for generating an internal address; and an associative memory means for generating first and second page addresses of the physical address based on the page address of the logical address and the page address of the segment base address; selection means for selecting one of the first and second page addresses generated from the associative memory means based on the carry output of the addition means; and the page address selected by the selection means and the page address generated from the addition means. 1. An address translation device comprising: a physical address register that stores an address within a page.