JPS628244A - Control system for virtual memory - Google Patents

Abstract

PURPOSE:To respond with an address conversion by the enlargement of an actual storage area by providing the actual storage area of integer-fold as large as the capacity of a virtual memory and allocating a virtual storage space only to a regulated actual storage area determined with its space identifier. CONSTITUTION:In the address conversion, an actual address below an actual page address can be obtained at a register 16, and an enlargement address generating part 21, with obtaining an enlargement address bit from the space identifier of a space register 10, sets it at an enlargement address register 20. The high-order of the register 16 to which the enlargement address register 20 is linked accesses to a memory device as the actual address. The enlargement address generating part 21 holds the C bit value of a segment table 13 or an address conversion table 17 at a latch 22, and controls the input gate of the enlargement address register 20, setting a regulated value at the register 20 when the bit value is 1.

Description

[Detailed Description of the Invention] [Summary] This is a virtual memory control method for converting a virtual memory address into a real address in a computer system. The virtual memory is configured to be divided into spaces with a fixed storage capacity. By providing a storage device with a real storage area that is an integral multiple of this storage capacity and allocating each virtual storage space only to a certain real storage area determined by its space identifier, address conversion when the real storage area is expanded is handled. can do.

[Industrial application field]

The present invention relates to a virtual memory control method for converting virtual memory addresses into real addresses in a computer system.

Due to improvements in the performance-to-price ratio of computer systems, etc.
□With the expansion of computer usage areas, both the size and number of programs used in each computer system have increased significantly.

In response to this trend, known virtual memory methods
:In expressions, a method is widely used to expand the storage area for programming by using the so-called multiple virtual storage method, which consists of multiple spaces.

In order to efficiently operate a system in which the virtual storage area has been expanded in this way, the storage area of the actual storage device, that is, the real storage area, must also be expanded appropriately.

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram illustrating one type of virtual storage. In the figure, each box represents one virtual storage space 1,
Each storage space is identified, for example, by a space identifier O11-n.

Each storage space 1 has a capacity of, for example, 16 MB (megabytes), and therefore a relative address within each space can be specified by a 24-bit address.

Each storage space is allocated to each job, but has a shared area 2.3 as shown in the figure, and the shared area 2.3 stores system control programs, control blocks, programs shared by the system, etc. This area is an area that holds the same content common to all storage spaces. The job area 4 is an area unique to each storage space. .

FIG. 3 is a block diagram showing an example of the configuration of an address translation mechanism.

When passing execution control to a job that has been allocated a certain storage space, the system control program registers space register 1.
Set the space identifier of the storage space to 0. Further, the control register 11 is set with the starting real address of the segment table area defined by the system.

Generated by the executed program and stored in register 12
The virtual address set to is, for example, a 24-bit address that represents a relative address within the storage space.

For example, the configuration of a virtual address is such that the upper 8 bits (bits 0 to 7) are the segment number, and the next 5 bits (bits 8 to 7) are the segment number.
12) is the page number, these 13 bits (bits θ to 12) constitute the page address of the 2KB (kilobyte) page, and the remaining 11 bits (bits 13 to 12) constitute the page address of the 2KB (kilobyte) page.
23) specifies the intra-page displacement.

When accessing a storage device, the virtual address is converted into a real address and the address of the storage device is specified. For this purpose, the system control program configures the required segment table 13 and page table 14 on the storage device in a known manner.

In this example, the segment table 13 is held in a storage area specified by the starting real address of the control register 11, and the segment table of each storage space is stored at an address obtained by adding a displacement of space identifier x 1024 to the starting address, for example. In this case, the segment table of each space has 256 4-byte entries 14 for each segment.

Each entry 14 of the segment table has a column for the page table start address and control information, and the control information includes a ■ bit that indicates the validity of the entry, and a segment belonging to the shared area 2.3 mentioned above. Contains a C bit to indicate that.

When the I bit in the control information is 1, the page table head address in item 14 points to the head of page table I5. Here, each entry in the segment table generally points to a different page table, but if the C bit is 1, the corresponding entries in each segment table all point to the same page table. .

As is well known, each page table 15 is a table in which each entry corresponds to each page of the virtual storage space and indicates the real address of the storage device where a copy of the page is placed.In this example, there are a maximum of 32 pages. It has a configuration that specifies the real page address of a 2KB page.

Address conversion is performed by determining the start address of the segment table of the space using the space identifier of the space register 10, and converting one item 14 in the segment table to the register 1.
The page address of bits 0 to 12 of register 12 is determined by the segment number of bits 0 to 7 of register 12, and one item in page table 15 specified by term 14 is determined by the page number of register 12. is converted into a real page address held in that entry in the page table.

The real address is obtained in the register 16 by setting the real page address in bits 0 to 12 of the register 16 and setting the intra-page displacement of the register 12 in bits 13 to 23.

As is well known, the real address obtained in this way is
So-called address translation buffer 1 called TLB etc.
7 and indexing directly from the page address of the register 12 speeds up address translation.

For example, in each term of the address translation buffer 17, the translated and output real page address and the space identifier in the space register IO at that time are stored, and in address translation, the space identifier of the term read by the page address is If it matches the space identifier in the space register 10 at that time, the real page address held there is used as the conversion result.

Note that each term in the address translation buffer 17 has a C bit with the same meaning as above, and when converting an address, if the C bit is 1, the real page address is valid regardless of the space identifier mismatch. shall be.

When a real address is determined by such an address translation buffer 17, the real page address obtained from the address translation buffer 17 is sent to the register 16 without executing the access to the segment table and page table described above. , and thereafter are controlled in the same manner as described above.

With the above configuration, virtual address translation is extended to a configuration with multiple storage spaces, but if the storage device is made larger than 16 MB to accommodate this, and therefore a real address with a bit number exceeding 24 bits is When trying to realize the required configuration, the segment table 13,
Since the bit width of each real address held in the page table 15, address translation buffer 17, etc. is all expanded, it is generally necessary to change their structure.
The scope of influence of the changes became large, and this became an obstacle when expanding the real storage area.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 20 is an extended address register, and 21 is an extended address generator.

[For production]

The storage device area allocation function of the system control program divides the storage device area into 16 MB areas sequentially from the first address, and only 6 for each virtual storage space and a specific 16 MB area determined by its space identifier. shall be assigned.

In this way, each entry in each page table and address translation buffer contains the above 16 addresses as real page addresses.
Store the relative address within the M B area.

Address translation is performed in the same manner as before, register 1
6, obtain the real address below the real page address.

At the same time, the extended address generation unit 21 generates the space register 10
A predetermined extension address determined at will is generated from the space identifier of As the address,
Used for storage access.

The extended address generation unit 21 generates a segment table.
1 or by the C bit of the address translation table.
When it is detected that the access destination is a shared area, a fixed address value (
For example, 0) is generated and set in the extension register 20.

As described above, expansion of the real storage area can be easily realized.

〔Example〕

In FIG. 1, a segment table 13, a page table 14, an address translation buffer 17, etc. have the same configuration as in the conventional example described above, and address translation is executed under the same control. However, the segment table 13, page table 15, etc. are stored in, for example, the first 16 MB of the storage device.
The extended address register is set to 9X area, and therefore, when accessing the storage device in the address conversion process, the extended address register is set to 0.

The storage device area allocation function of the system control program manages the storage device area by dividing it into 16 MB areas sequentially starting from the first address, and for each virtual storage space, a specific area determined by its space identifier is assigned. Allocate only 16MBe1 area.

For example, assume that the lower bits of the space identifier are used as the index of this 16MB11 area.For example, if the space identifier is 8 bits, the lower 4 bits are used for this. This number of bits may be set for each system.

The system control program allocates the space identifier numbers of the virtual storage spaces in consideration of the allocation area limit set in this manner so that the entire area of the storage device is used as uniformly as possible.

In this way, the address of the 16MB51 area is uniquely determined from the space identifier, so that each address is uniquely determined from the space identifier.

Each section of page table and address translation buffer contains
Is the above 16MB the actual page address? It is only necessary to store the relative address within the J area, and therefore it can be expressed using the same number of bits as before.

Address translation is performed in the same manner as before, register 1
At the same time, the extended address generator 21 generates an extended address, which is constructed by extracting, for example, the lower 4 bits of the space identifier of the space register 10, into the extended address register 20. set.

As shown in the figure, an extended address register 20 connected above the register 16 is used as an extended real address for accessing the storage device.

The extended address generation unit 21 stores the value of the C bit in the segment table 13 or the address conversion table 17 in latch 2.
2 and control the input gate of the extended address register 20, and if the value is 1 (indicating a shared area),
Regardless of the contents of the space register 10, a constant address value (for example, 0) is set in the extension register 20.

With the above configuration, it is possible to deal with expansion of the real storage area without having to significantly change the address translation mechanism.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the real storage area can be expanded relatively easily in a computer system using a virtual storage method. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of an example of a virtual storage system, and FIG. 3 is a block diagram of a configuration example of a conventional address translation mechanism. In the figure, l is the storage space, 2.3 is the shared area, 4 is the job area, 10 is the space register, 11 is the control register,
12.16 is a register, 13 is a segment table, 15 is a page table, 17 is an address translation buffer, 20 is an extended address register, 21 is an extended address generator

Claims (1)

[Claims] A virtual address that is divided into a plurality of storage spaces each having a predetermined capacity and constituted by a space identifier of the storage space and a relative address within the storage space is an integral multiple of the predetermined capacity. When converting the relative address (12) into a real address of a storage device that has a storage area and holds the data specified by the virtual address, convert the relative address (12) into a partial address (16) that forms part of the real address. address conversion means (13, 15, 17) for converting; and means (21) for expanding the partial address by concatenating the partial address (16) with an address (20) determined as a predetermined function of the space identifier; A virtual memory control method characterized by having the following.