JP2000357123A - Memory access control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access a memory without being aware of the border of a storage area by converting a decomposed address into an address of the storage area and accessing addresses including the border of the storage area. SOLUTION: A memory map address converting circuit is composed of an address decomposing means 300, an address converting means 301, a storage area access means 302, a data decomposing means 310, a data merging means 311, and a fixed writing means 320. To read data out, an address 3b and an access size 3c are inputted to the address decomposing means 300 first and the address decomposing means 300 outputs an address 3e to be accessed. The address converting means 301 searches a storage area mapping management table for a storage area mapped to the outputted address 3e outputted to the address decomposing means 300. Then the address 3g of the storage area to be addressed is calculated from the head address of the set storage area and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control system for managing a memory access area of a computer system and performing memory access.

[0002]

2. Description of the Related Art Generally, in a computer system, a plurality of storage areas are accessed by mapping them in a memory address space. For example, Japanese Patent Laying-Open No. 9-22377 discloses an example of a memory map address conversion circuit that maps a plurality of storage areas to a memory address space. FIG. 14 is a block diagram showing a configuration of such a conventional memory map address conversion circuit, and FIG. 15 is a block diagram showing a configuration of an address map generation circuit of the memory map address conversion circuit shown in FIG. As shown in FIG. 14, the memory map address conversion circuit 8 includes an address map generation circuit 10, 4-bit D latches 12a, 12b, 12c, 12d, 4-bit comparators 20a, 20b, 20c, 20d, and a 4-input OR gate 30. , And a two-input OR gate 32a, 32
b.

Hereinafter, the mapping setting shown in FIG. 15 and the actual operation of memory access will be described with reference to the memory map address conversion circuit shown in FIG. At the time of system startup or during memory remapping processing, a memory select signal, a clock, and a start signal are input to the memory map address conversion circuit 10. The 16 select signals correspond to the address spaces 100 to 115 divided into 16 in the memory address space shown in FIG. FIG.
In the example shown in (1), the address spaces for the selected memory are 101, 104, 106, and 114, and the select signal is 0100000001010010 in binary. The memory map address conversion circuit 10 stores the value of the upper 4 bits of the specified memory address space into the 4-bit D latch of 12a to 12d in binary notation 000, respectively.
1, 0100, 0110, and 1110 are set. In addition,
Detailed operation of the setting is omitted here.

[0004] Next, an operation in memory access will be described. The upper four bits of the 24-bit address signal output by the CPU are input to the 4-bit comparators 20a to 20d as AI (23:20), and are output to the AI (19:
0), the lower 20 bits input as A
This is a configuration that is output as O (19: 0). And
Above this AO (19: 0), a two-input OR gate 32
AO (21) output from a and a two-input OR gate 32
AO (20) output from b is added to make a 22-bit memory address signal.

That is, when AI (23:20) is 0001 in binary, the E of the 4-bit comparator 20a is
The Q signal becomes active, but this EQ signal is
Since it is not input to the R gates 32a and 32b, AO (2
0) and AO (21) are both 0. Therefore, as the address signal output from the memory map address conversion circuit 8, the upper two bits are both 0, and the lower 20 bits are AI (19: 0) as they are.
0). The address of this address signal is 0xxxx (x is any of 0 to F) in hexadecimal and is mapped to the area 200.

When the operation of the memory map address conversion circuit 8 is performed by software, each of the storage areas 200 to 20
An area for holding the signal of the upper 4 bits is secured in 3, and the upper 4 bits of the address space for the memory to be mapped are set. When accessing the storage areas 200 to 203, a storage area that matches the value of the upper 4 bits of the specified memory address is selected, and access processing is performed using the lower 20 bits of the address.

[0007]

However, in the above conventional example, the first problem is that when a storage area is accessed by a converted address, data in another storage area may be accessed. In other words, if the memory access is a write, the data is destroyed. The reason is that the address of the storage area to be accessed is obtained by converting the head of the address, but the access range may extend over the boundary of the storage area because the access size is not considered.

A second problem is that, in a computer system, the same storage area is mapped to an address space for a different memory, for example, one address is managed by a cache and the other is not managed by the cache. Although it is necessary, the conventional management method described above cannot map the same storage area to a plurality of memory address spaces. The reason is,
This is because, instead of mapping the storage area to the memory address space, the memory address space is mapped to the storage area, and the storage area can only be mapped to one memory address space.

A third problem is that the head of the storage area to be mapped is not a multiple of the mapping size,
If it is not continuous, it will not work properly. The reason is that the storage area in units of mapping size starting from 0 is fixedly assigned by the 4-bit comparator that matches the start address of the storage area.

A fourth problem is that, in software simulation, a process of returning fixed data may be required in a read process of a space in which a storage area is not mapped in a memory address space. Is required separately from normal access processing, and its operation must be verified, which complicates the access processing. Further, the first problem is that if the next storage area does not exist at the boundary of the storage area, the simulation ends abnormally with a core dump. The reason is that there is no accessible area in the memory address space to which the storage area is not mapped.

A fifth problem is that it is necessary to perform a process conscious of the data type of the computer system and verify its operation. The reason is that when the data type of the computer system to be simulated is different from the data type of the computer system for performing the simulation, a process of converting the data type is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory access control system capable of mapping a plurality of storage areas to a memory address space and enabling memory access without being aware of the boundaries of the storage areas. Another object of the present invention is to provide a memory access control system capable of mapping the same storage area to a plurality of different memory address spaces. It is still another object of the present invention to provide a memory access control system capable of eliminating the restriction on the start address of a storage area and mapping even if the storage areas are not continuous.

Still another object of the present invention is to provide a memory access control system capable of performing data access by the same processing as ordinary memory access even when a storage area is not mapped in a memory address space. It is in. Still another object of the present invention is to provide a memory access control system capable of performing access processing independent of data types of a computer system to be simulated and a computer system executing a simulator.

[0014]

In order to achieve the above object, the present invention provides a mapping means for mapping a storage area in a memory address space based on a predetermined mapping size, and a method for mapping a memory access address and an access size. Address decomposing means for decomposing the access address, and address translating means for translating the decomposed access address into an address of the storage area, wherein an address including a boundary of the storage area is accessed. Features. Therefore, a plurality of storage areas can be mapped in the memory address space, and memory access can be performed without being aware of the boundaries of the storage areas, thereby preventing data destruction during writing.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. The embodiment of the present invention, when simulating a computer system with software, in the process of mapping a plurality of storage areas in the address space for the memory of the computer system to perform the simulation, and accessing the data of each storage area, In particular, access including storage area boundaries, mapping of the same storage area to address spaces for different memories, access to address space for memories where storage areas were not mapped, execution of target computer system and simulation software The present invention provides a memory access control system that does not depend on the data type of a computer system.

FIG. 1 is a block diagram showing a memory map address conversion circuit according to a first embodiment of the present invention, and FIG. 2 shows a storage area mapping management table in the memory map address conversion circuit shown in FIG. FIG. FIG. 3 is an explanatory diagram showing a mapping example in the memory map address conversion circuit shown in FIG.
FIG. 4 is an explanatory diagram showing the contents of a storage area mapping management table in the memory map address conversion circuit shown in FIG. 1, and shows a configuration example corresponding to the mapping example shown in FIG. FIG. 5 is a block diagram showing a state of the memory map address conversion circuit shown in FIG. 1 when data is read, and FIG. 6 is a block diagram showing a state of the memory map address conversion circuit shown in FIG. 1 when writing data. FIG. FIG. 7 is an explanatory diagram showing differences in memory data due to differences in data types.

The memory map address conversion circuit according to the present embodiment includes an address decomposition unit 300 and an address conversion unit 3.
01, a storage area access unit 302, a data division unit 310, a data combination unit 311, and a fixed value writing unit 320. Address translation means 3
01 is the storage area mapping management table 4 shown in FIG.
The address for the memory is converted to the address of the storage area using the data of 00. The fixed value writing means 320 is used for data reading, and the storage area is mapped to a memory address space at a position offset from the head of the storage area specified by the address of the storage area converted by the address conversion means 301. Change the data in the storage area that is used when not performed to a fixed value.

Next, the overall operation of the present embodiment will be described in detail with reference to FIG. 1, FIG. 2, FIG. 5, and FIG. First, the memory address space is divided by the mapping size, and the storage area mapping management table 400 having the divided number of tables is secured. Next, one storage area 520 for the mapping size is secured, and the start address thereof is set as an initial value of the storage area mapping management table. Further, the storage areas 530 to 53 are used for the memory address space in which the mapping of the storage area 520 is specified.
No. 3 is secured, and the address is set in a corresponding part of the storage area mapping management table 400. If the mapping of the storage area for which the area is already secured is specified, the storage area is not secured and only the address setting in the mapping management table 400 is performed. This completes the storage area mapping process.

FIG. 5 shows only the means necessary for reading data from FIG. 1 by solid lines. First, the address (3b) and the access size (3c) are input to the address resolving means 300. The address resolving means 300
The address (3e) to be accessed is output, and if the access size (3c) is not 1 byte, the address (3e) to be accessed next is output again. Address translation means 3
01, a storage area mapped to the address (3e) output to the address resolving means 300 is searched from the storage area mapping management table 400, and the address (3g) of the storage area to be accessed from the head address of the storage area set therein. ) Is calculated and output.

The fixed value writing means 320 obtains an offset from the head of the storage area from the address (3g) in the read request (3a), and sets a fixed value used when the storage area is not mapped to the offset of the storage area. , And output as address (3h). The storage area access unit 302 reads the data of the storage area specified from the address (3h) and the read request (3a), and outputs the read data (3i). The data combining unit 311 waits until the read data (3i) becomes equal to the access size (3c) from the read request (3a). If the access size (3c) is not 1 byte, an access to the storage area occurs again at the address (3e) output from the address resolving means 300, and the read data (3i) is output. When the data size of the read data (3i) matches the number of bytes of the specified access size (3c), the data combining means 311 combines the data into the data format of the computer system of the simulation target, and By outputting 3k), the data reading process ends.

FIG. 6 shows only the means necessary for writing data from FIG. 1 by solid lines. First, the address (3b) and the access size (3c) are input to the address resolving means 300. The address resolving means 300 outputs the address (3e) to be accessed and, if the access size is not 1 byte, the address (3e) to be accessed next.
e) is output again. The address conversion means 301 searches the storage area mapping management table 400 for a storage area mapped to the address (3e) output from the address decomposing means 300, and searches for a storage area to be accessed from the head address of the storage area set there. Address (3
g) is calculated and output to the fixed value writing means 320.

The output address (3g) is directly input to the address (3g) by the fixed value writing means 320.
h). Access mode (3a)
, The access size (3c) and the data (3d) are input to the data decomposing means 310, and the first data (3f) is output in the data format of the simulation target computer system. If the access size (3c) is not 1 byte, the remaining data (3c)
f) is output again. The storage area access unit 302
From the write request (3a) to the address of the storage area (3h)
The data (3f) is written to. Access size (3c)
Is not one byte, the address (3e) output from the address resolving means 300 and the data (3f) output from the data resolving means 310 are written to the storage area.

Next, effects of the present embodiment will be described. In the present embodiment, since the access address is divided by the access size and all the addresses are converted, the address including the boundary of the storage area can be accessed, and the mapping of the storage area can be managed. By setting the start address of the same storage area in the table to be mapped, the same storage area can be mapped to the address space for different memories, and each storage area is managed by the start address. The restriction that the regions must be continuous is eliminated.

In this embodiment, since the storage area is mapped by default in the memory address space to which the storage area is not mapped, the memory address to which the storage area is not mapped is set. Since you can access the space and always write a fixed value,
The read data becomes a fixed value. Further, since the access data is converted into the data type of the computer system of the simulation target by the data decomposing unit 310 and the data combining unit 311, it is not necessary to perform the processing depending on the data type of the computer system executing the simulation.

Next, the operation of this embodiment will be described using a specific example. As shown in FIG. 3, the address space 500 for the memory has an address range from 0000h to FFFFh and is divided into 16, so that the mapping size of each storage area is 1000h. FIG. 4 shows the contents of the storage area mapping management table 600 after the mapping. Before the mapping, the address 1000h of the storage area 520 secured with the size of 1000h is set in each of the setting areas 601 to 616 as the initial value. It is assumed to be set as

Next, a mapping process is performed. In FIG. 3, the storage area 530 and the address space 50 are stored in the address space 502.
4, storage area 531 and address space 507, storage area 5
30, the storage area 532 is mapped to the address space 509, the storage area 533 is mapped to the address space 512, and the storage area 532 is mapped to the address space 515. Further, address spaces 501, 503, 505, 506, 508, 51
0, 511, 513, 514, and 516 are storage areas 52
0 is mapped. Also, from 601 to 6 in FIG.
The start address of each storage area is set in the 16 management tables.

The method of mapping is not limited to the method of storing the head address of the storage area as described above. For example, the management table 600 is set by designating a page indicating each divided address space of the memory address space and the number of the storage area. If the number of the storage area is 0, a new storage area is set. May be input, and the number of the reserved storage area may be input as the other storage area number. For example,
To perform the mapping of FIG. 3, page 1 and number 0, page 3 and number 0, page 7 and number 1, page 8 and number 0,
Page 11 and number 0, page 15 and number 3, and so on.

Next, returning to FIG. 1, the memory address 6
When 4 bytes of data are read from 004h, the address mode (3a) in FIG. 1 is read and the address (3b) is read.
Is 6004h and the access size (3c) is 4 bytes. The address resolving means 300 to which the address (3b) and the access size (3c) are input outputs the head address 6004h as the address (3e). The address conversion means 301 which has fetched the address of 6004h from the address (3e) reads the storage area 5 mapped to 6004h from the storage area mapping management table 600.
30 start address 2000h and offset 004h
Is output as an address (3g). Since the access mode (3a) is read, the offset from the head of the storage area of the address (3g) is 004h excluding the upper 4 bits of the address used to divide the memory address space into 16, and the fixed value is written. The means 320 is configured to store 10 of the storage area 520 at that position.
Write fixed value (FFh) to 04h, 2004 to 3h
Output h.

The storage area access means 302 responds to the read request (3a) with the address 200 from the address (3h).
The data in the storage area of 4h is read and output as read data (3i). Similarly, the addresses of 6005h, 6006h, and 6007h output as the address (3e) are 2005h, 2006h, and 20h, respectively.
Is converted to 07h, data is read from the storage area, and output as read data (3i). As shown in FIG. 7, when the data type of the computer system of the simulation target is big endian, the data combining unit 311 that has fetched the 4-byte data by the read data (3i) causes the first data to be the highest order. , Register 900 and address memories 910-9
13 are arranged and output as data (3k). In the case of a simulation of a little-endian computer system, the register 901 and the address memory 920 are set so that the first data becomes the lowest.
The data is arranged using 923 and output as data (3k).

When the access mode (3a) is write, the data decomposing means 310 starts from the highest data when the simulation target computer system is big endian, and starts with the lowest data when little endian. , Data (3f). Further, in the case of a storage area used for a space where the storage area to be read is not mapped, since the data is always written with a fixed value (FFh) by the fixed value writing means 320, the data does not become a value other than the fixed value.

As described above, according to the memory access control system of the present embodiment, the following effects can be obtained. (1) Since all addresses to be accessed are converted, there is an effect that addresses including the boundaries of storage areas can be accessed. (2) Since the storage area can be mapped in the memory address space, the same storage area can be mapped in a plurality of memory address spaces. (3) Since the storage area is managed at the start address of each storage area, there is no limitation on the start address of the storage area, and there is no need for each storage area to be continuous. (4) Since the accessible storage area is set as the initial value of the mapping, it is possible to access the memory address space to which the storage area has not been mapped. (5) Since the access data is converted into the data type of the computer system of the simulation target at the time of writing and at the time of reading, processing can be performed without considering the difference in data type.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 shows a second embodiment of the present invention.
FIG. 9 is a block diagram showing a memory map address conversion circuit according to the embodiment, and FIG. 9 is an explanatory diagram showing a mapping example in the memory map address conversion circuit shown in FIG. FIG. 10 is an explanatory diagram showing the contents of the storage area mapping management table in the memory map address conversion circuit shown in FIG. 8, and shows a configuration example corresponding to the mapping example shown in FIG. FIG. 11 is a block diagram showing a state when data is read by the memory map address conversion circuit shown in FIG. 8, and FIG. 12 is a block diagram showing a state when data is written by the memory map address conversion circuit shown in FIG. FIG. FIG. 13 is an explanatory diagram showing a storage area mapping management table in the memory map address conversion circuit shown in FIG.

The memory map address conversion circuit according to the present embodiment includes an address decomposition unit 300 and an address conversion unit 30.
3, a storage area access unit 302, a data dividing unit 310, and a data combining unit 311. The address conversion means 303 has a storage area mapping management table for reading and writing as shown in FIG. 13, and switches between the management tables according to the access mode to change the memory address to the address of the storage area. Convert to

Next, FIG. 8, FIG. 11, FIG. 12, and FIG.
The overall operation of the present embodiment will be described in detail with reference to FIG. First, the memory address space is divided by the mapping size, and a storage area mapping management table (FIG. 13) having the divided number of tables is secured. Next, two storage areas of the mapping size are secured, and the start address of one storage area is set as the initial value of the management table 1500 for reading, and the start address of the other storage area is set as the initial value of the management table 1550 for writing. Set each. Here, the data in the storage area set in the management table for reading is initialized with a fixed value. Further, a storage area is reserved for an address space for the memory to which the mapping of the storage area is designated, and the address is set in a corresponding portion of the management table for reading and writing. When the mapping of the storage area in which the area is already secured is designated, the storage area is not secured, and only the address setting to the mapping management tables 1500 and 1550 is performed. This completes the storage area mapping process.

FIG. 11 shows only means necessary for reading data from FIG. 8 by solid lines. First, an address (3b) and an access size (3c) are input to the address decomposing means 300. The address resolving means 300 outputs the address (3e) to be accessed and, if the access size is not 1 byte, the address (3e) to be accessed next.
e) is output again. The address converting means 303 outputs the address (3e) output from the address resolving means 300.
In the access mode (3
Since a) is for reading, the reading management table 150 is used.
The address of the storage area to be accessed is calculated from the start address of the storage area set there, and is output as the address (3g).

The storage area access means 302 reads the data of the storage area specified from the address (3g) and the read request (3a), and outputs it as data (3i). The data combining unit 311 waits for data from the read request (3a) to the data (3i) until the data becomes the access size (3c). If the access size (3c) is not 1 byte, access to the storage area occurs again at the address (3e) output from the address resolving means 300, and data (3i) is output. The number of data output as data (3i) and the specified access size (3
When the byte numbers in c) match, the data combining means 3
Numeral 11 combines the data into the data format of the computer system of the simulation target and outputs the data (3k)
And the data reading process ends.

FIG. 12 shows only means necessary for writing data from FIG. 8 by solid lines. First, an address (3b) and an access size (3c) are input to the address decomposing means 300. The address resolving means 300 outputs the address to be accessed (3e) to the address (3e).
e) is calculated and output again. Address conversion means 303
Since the access mode (3a) is the write mode, the storage area mapped to the address (3e) output from the address resolving means 300 is searched from the write management table 1550, and the start address of the storage area set there is set. Calculate the address of the storage area accessed from
Output the address (3g).

Further, the write mode of the access mode (3a), the access size (3c) and the data (3d) are input to the data decomposing means 310, and the first data (3f) in the data format of the computer system of the simulation target is output. Is done. If the access size (3c) is not 1 byte, the remaining data (3f)
Is output again. The storage area access unit 302 writes the data (3f) from the write request (3a) to the address (3g) of the storage area. If the access size (3c) is not 1 byte, writing to the storage area is performed using the address (3e) output from the address decomposing means 300 and the data (3f) output from the data decomposing means 310.

Next, effects of the present embodiment will be described. In the present embodiment, since the access address is divided by the access size and all the addresses are converted, the address including the boundary of the storage area can be accessed, and the mapping of the storage area is managed. By setting the start address of the same storage area in the table, it is possible to map the same storage area to different memory address spaces. By managing each storage area with its own start address, the start address of the storage area And that the storage areas must all be continuous.

In this embodiment, since the storage area is mapped by default in the address space for the memory where the storage area is not mapped, the address for the memory where the storage area is not mapped is set. Access to space. Further, since the access data is converted into the data type of the computer system of the simulation target by the data decomposing unit 310 and the data combining unit 311, it is not necessary to perform the processing depending on the data type of the computer system executing the simulation. Further, in the present embodiment, since the storage area for the address space for the unmapped memory is switched between for reading and for writing, it is always set to the initial value when reading the unmapped address. The read fixed value can be read.

Next, the operation of this embodiment will be described using a specific example. As shown in FIG. 9, since the memory address space 1100 has an address range from 0000h to FFFFh and is managed by dividing it into 16, the mapping size of the storage area is 1000h. FIG.
Is the storage area mapping management table 1 after mapping
Although the contents of 200 and 1220 are shown, before the mapping, 1201 to 1216 have a size of 100
Start address 100 of storage area 1120 secured at 0h
It is assumed that 0h is set as an initial value, and a head address 3000h of the storage area 1121 secured with a size of 1000h is set as an initial value from 1220 to 1236.

Next, a mapping process is performed. In FIG. 9, the storage area 1130 in the address space 1102, the storage area 1131 in the address space 1104, the storage area 1130 in the address space 1107, and the storage area 1130 in the address space 1109.
132, a storage area 1133 is mapped to the address space 1112, and a storage area 1132 is mapped to the address space 1115. The other address spaces are mapped to the storage area 1120 when reading data, and to the storage area 1121 when writing data. The mapping method is not particularly limited as described in the first embodiment.

When writing 2 bytes of data 1234h to 1FFFh of the memory address, the access mode (3a) of FIG. 8 is written and the address (3b) is 1FFF.
The h access size (3c) is 2 bytes, and the write data (3d) is 1234h. The address resolving means 30 to which the address (3b) and the access size (3c) are input
0 is the first address 1FFFh as the address (3e)
Is output. Since the access mode (3a) is read, the address conversion means 303 that has fetched the address of 1FFFh from the address (3e) converts the address using the write management table 1220. Top address 100h from read management table to storage area
Is calculated from the address (3e) by masking the most significant 4 bits, and the address FFh to the storage area is output as the address (3g).

The data decomposing means 310 takes in the write address mode (3a), the access size of 2 bytes, and the data to be written (3d) 1234h. When the data type of the computer system to be simulated is little endian, 34h is output as data (3f) based on FIG. 7, and when it is big endian, 12h is output as data (3f). The storage area access means 302 sets the data to be written from the access mode (3a), the address FFFh from the address (3g) to the storage area, and the data to be written from the data (3f). Since the access size is not 1 byte, the next address (3e) and data (3f) are output, and a value is written to the address 20000h of the storage area. Here, in the data reading of the 1FFFFh address, since the management table used for the conversion in the address conversion 303 is different,
The address of the storage area to be accessed is 1FFFh, and a fixed value is always read.

As described above, according to the memory access control system of this embodiment, the following effects can be obtained. (1) Since all addresses to be accessed are converted, there is an effect that addresses including the boundaries of storage areas can be accessed. (2) Since the storage area can be mapped in the memory address space, the same storage area can be mapped in a plurality of memory address spaces. (3) Since the storage area is managed at the start address of each storage area, there is no limitation on the start address of the storage area, and there is no need for each storage area to be continuous. (4) Since the accessible storage area is set as the initial value of the mapping, it is possible to access the memory address space to which the storage area has not been mapped. (5) Since the access data is converted into the data type of the computer system of the simulation target at the time of writing and at the time of reading, processing can be performed without considering the difference in data type. (6) Since the storage area for the address space for the unmapped memory is configured to be switched between read and write, the fixed value set to the initial value is always read when reading the unmapped address. be able to.

[0046]

As described above, in the memory access control system of the present invention, the storage area is mapped in the memory address space, the address is decomposed from the memory address and the access size, and the decomposed address is decomposed. Is converted to the address of the storage area,
Access to addresses including storage area boundaries is now performed. Therefore, a plurality of storage areas can be mapped to a memory address space, and memory access can be performed without being aware of the boundaries of the storage areas, and data destruction during writing can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory map address conversion circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a storage area mapping management table in the memory map address conversion circuit shown in FIG.

FIG. 3 is an explanatory diagram showing a mapping example in the memory map address conversion circuit shown in FIG. 1;

FIG. 4 is an explanatory diagram showing the contents of a storage area mapping management table in the memory map address conversion circuit shown in FIG. 1;

FIG. 5 is a block diagram showing a state when data is read by the memory map address conversion circuit shown in FIG. 1;

FIG. 6 is a block diagram showing a state at the time of data writing of the memory map address conversion circuit shown in FIG. 1;

FIG. 7 is an explanatory diagram showing differences in memory data due to differences in data types.

FIG. 8 is a block diagram showing a memory map address conversion circuit according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a mapping example in the memory map address conversion circuit shown in FIG. 8;

FIG. 10 is an explanatory diagram showing the contents of a storage area mapping management table in the memory map address conversion circuit shown in FIG. 8;

11 is a block diagram showing a state when data is read by the memory map address conversion circuit shown in FIG. 8;

12 is a block diagram showing a state at the time of data writing of the memory map address conversion circuit shown in FIG. 8;

FIG. 13 is an explanatory diagram showing a storage area mapping management table in the memory map address conversion circuit shown in FIG. 8;

FIG. 14 is a block diagram showing a conventional memory map address conversion circuit.

15 is a block diagram showing a configuration of an address map generation circuit in which the memory map address conversion circuit shown in FIG. 14 is incorporated.

[Explanation of symbols]

300 address decomposing means 301 address converting means 302 storage area accessing means 310 data dividing means 311 data combining means 320
Fixed value writing means.

Claims (8)

[Claims] A mapping means for mapping a storage area in a memory address space based on a predetermined mapping size; an address decomposing means for decomposing the access address from a memory access address and an access size; Address conversion means for converting an access address into an address of the storage area, wherein an address including a boundary of the storage area is accessed. 2. The memory access control system according to claim 1, wherein said mapping means includes means for mapping said storage area in a memory address space to which no storage area is mapped. 3. The memory access control system according to claim 1, wherein said mapping means includes means for mapping the same storage area in different memory address spaces. 4. The memory access control system according to claim 1, further comprising conversion means for converting the data in the storage area into a data type of a computer system of a simulation target and processing the data. 5. The method according to claim 1, wherein the address of the read request is decomposed by the access size, each address is converted, and the data read from the storage area is finally read data by the data combining means. 5. The memory access control system according to 2, 3, or 4. 6. The method according to claim 1, wherein an address of the write request is decomposed by the access size, each address is converted, the write data is decomposed by the access size, and the data is written into the storage area. 3 or 4
A memory access control system as described. 7. The method according to claim 5, wherein the read request writes a fixed value to a storage area allocated to an address space for a memory to which a storage area has not been mapped.
A memory access control system as described. 8. A means for using different mapping between writing and reading, and mapping two storage areas to a memory address space to which no storage area is mapped, thereby preventing destruction of read data due to writing. Claims 1, 2, 3,
8. The memory access control system according to 4, 5, 6, or 7.