JP2001337909A - Pci bridge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PCI bridge resolving the lacking of the memory space of PCI in a system structure in which a plurality of PCI buses are connected together via the PCI bridge. SOLUTION: This PCI bridge is provided with a base address memory means 30 for a (primary) PCI bus 100 storing the base address of the first PCI bus 100, a converted base address memory means 33 for a (secondary) PCI bus 200 storing the converted base address to the second PCI bus 200, a (first) effective size memory means 31 storing the effective size from the base address indicated by the base address memory means 30 for the (primary) PCI bus 100, a (first) address comparing means 32 comparing whether the PCI address determined on the first PCI bus 100 lies in the effective size indicated by the (first) effective size memory means 31 or not based on the base address indicated by the base address memory means for the (primary) PCI bus 100, and a (first) address converting means 34 converting the address of the second PCI bus 200 with the converted base address memory means 33 for the (secondary) PCI bus 200 when the comparison results of the (first) address comparing means 32 coincide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PCI (Protocol C)
ontrol Information: protocol control information) bridge,
In particular, a PC for converting an address from a primary (first) PCI bus address space to a secondary (second) PCI bus address space
Regarding I-bridge.

[0002]

2. Description of the Related Art The prior art of such a PCI bridge is disclosed in, for example, JP-A-10-222457, JP-A-10-222457.
No. 0-247163 and JP-A-11-3282. In such a conventional PCI bridge, generally, the address space of the secondary PCI bus is
It is allocated in the address space of the I bus. Therefore, when connecting a plurality of PCI buses with a PCI bridge, the PC
There was a case where the address space of the I bus was insufficient. FIG.
Is an example of a conventional PCI bridge. PCI of FIG.
The bridge 300 includes a primary PCI bus 100 and a secondary P bus.
It is connected between the CI buses 200. Primary PCI bus 1
The first CPU (Central Processing Unit, hereinafter referred to as CPU)
(1)) and a plurality of I / O (input / output) cards 1
3 and 14 are connected. The first CPU (1) includes a processor 10, a memory 11, and a controller 12. On the other hand, the secondary PCI bus 200 has a second CPU
(2) and a plurality of I / O cards 23 and 24 are connected. Here, the second CPU (2) has the same configuration as the first CPU (1), and includes a processor 20, a memory 21, and a controller 22. PCI bridge 300
Are the base address storage means 30 for the PCI bus 100,
It comprises an effective size storage means 31 and an address comparison means 32. This PCI bridge 300 is a primary PC
The I bus 100 and the secondary PCI bus 200 are connected.

FIG. 10 shows the first CPU (1) shown in FIG.
Second CPU (2) and each I / O card 13, 14, 2
An example of 3, 24 PCI memory mapping is shown. The first CPU (1) connected to the primary PCI bus 100
The "address = 0" to "address = A-1" and the I / O card 13 is "address = A" to "address = B-1"
In addition, the I / O card 14 is set to “address = B” to “address = C−1”, and the PCI bridge 300 is set to “address = B”.
C "to" address = TOP ". Second CPU connected to secondary PCI bus 200
(2) is “address = C” to “address = D−1”
The I / O card 23 has “address = D” to “address = E−1”, and the I / O card 24 has “address = E”.
Each is mapped to “address = TOP”. At this time, the memory space of the secondary PCI bus 200 is
It is mapped in the memory space of the PCI bridge 300 of the bus 100, and “address = D” and “address =
“E” falls within the range of “address = C” to “address = TOP”.

[0004] Next, referring to FIG.
4 shows an operation example of the bridge 300. This PCI bridge 3
00, “m = 1024” and “n” in FIG.
= 2048 ". The first CPU (1)
"Address = C" is set in the base address storage means 30 for the PCI bus 100 of the CI bridge 300 (step S1). To the effective size storage means 31, "size = TOP"
-C "is set (step S2). When reading (reading) the data of the I / O card 23 from the first CPU (1), the first CPU (1) issues a data read request to the PCI bus 100, for example, at “address = C + 1056”. The PCI bridge 300 includes a base address storage unit 30 for the PCI bus 100 and an effective size storage unit 3.
1 and “address = C + 1056” are compared with the address comparing means 3
Compare with 2. If the comparison results match, the PC
A data read request is issued to the I bus 200 at "address = C + 1 056" (step S3). This address is
Since the address matches the range of “address = D” to “address = E−1”, the I / O card 23 responds to this address,
The read data is returned (step S4).

Similarly, when data is written from the first CPU (1) to the I / O card 24, the first
The CPI (1) issues a data write request at, for example, “address = C + 2112”. The PCI bridge 300
PCI bus 100 base address storage means 30 and effective size storage means 31 and "address = C + 2112"
Are compared by the address comparing means 32. If the comparison results match, the PCI bus 200 sends “address = C +
At 2112 ", a data write request is issued. Since this address matches the range of “address = E” to “address = TOP”, the I / O card 24 responds to this address and receives write data (step S5).

When data is written from the I / O card 24 of the PCI bus 200 to the memory 11 of the first CPU (1), the I / O card 24 issues a data write request, for example, at "address = 0". PCI bridge 300
Issues a data write request to the primary PCI bus 100 because “address = 0” is outside the range of “address = C” to “address = TOP”. Since this address matches the range of “address = 0” to “address = A−1”, the first CPU (1) responds to this address and writes the write data to the memory 11 (step S6).

[0007]

However, in the above-described prior art, the address space of the secondary PCI bus is generally one.
When the I / O card connected to the secondary PCI bus requires a large PCI memory space because of allocation in the address space of the next PCI bus, there is a problem that the PCI memory space is insufficient. Similarly, when a plurality of PCI buses are connected by a PCI bridge, the number of I / O cards increases. Even if the PCI memory space required by each I / O card is small, a PCI memory space for several I / O cards or the like is required, so that there is a problem that the address space of the PCI bus is insufficient.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the shortage of the PCI address space even if the PCI bus is extended via a PCI bridge, and to extend the PCI address space to several times the PCI bus as a whole system. To provide a possible PCI bridge.

[0009]

A PCI bridge according to the present invention is connected to a first PCI bus and a second PCI bus, and stores a base address of the first PCI bus.
CI bus base address storage means, first effective size storage means for storing an effective size from the base address indicated by the first PCI bus base address storage means, and a PCI address determined on the first PCI bus stored in the first effective size storage area. First comparing and judging from the base address indicated by the means whether it is within the effective size indicated by the first effective size storage means;
A second PCI bus conversion destination base address storage means for storing a second PCI bus conversion destination address; and a second PCI bus conversion destination base address storage means and a first address comparison means. First address conversion means for obtaining a second PCI bus address based on the output.

Further, according to a preferred embodiment of the present invention, the first address conversion means, when the comparison result of the first address comparison means matches, the address on the first PCI bus and the first PCI bus base address storage means. Of the base address of the second PCI bus, and adds the result to the base address of the second PCI bus.
Find the address of the I bus. A plurality of I / O cards are connected to the second PCI bus, and the memory space of the first PCI bus allocated to the PCI bridge is allocated to the plurality of I / O cards by the first address conversion means. Based on a second PCI bus base address storing means for storing a second PCI bus base address, a second effective size storing means for storing an effective size, and based on the second PCI bus base address storing means and a second effective size storing means. Second address comparing means for comparing addresses. A second address conversion means for receiving a match output from the second address comparison means and converting it to a first PCI bus address; and a first PCI bus conversion destination for outputting a first PCI bus conversion destination base address to the second address conversion means. A base address storage unit; The first and second address translating means are respectively connected to a second PC
It is connected to the I bus and the first PCI bus.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a PCI bridge according to the present invention will be described below in detail with reference to the accompanying drawings. Incidentally, among the components in the present invention, the components corresponding to the components of the prior art, for convenience,
Similar reference numbers are used.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a PCI bridge according to the present invention. This PCI
The bridge 300 is connected between the primary (first) PCI bus 100 and the secondary (second) PCI bus 200. To the primary PCI bus 100, a first CPU (1) including a processor 10, a memory 11, and a controller 12, and a plurality of I / O cards 13, 14 are connected.
Further, a plurality of I / O cards 23 and 24 are connected to the secondary PCI bus 200. PCI bridge 300
Is a (secondary) PCI bus 200 in addition to the (primary) PCI bus 100 base address storage means 30, the (first) effective size storage means 31, and the (first) address comparison means 32.
Conversion destination base address storage means 33, (first) address conversion means 34, (secondary) base address storage means 35 for PCI bus 200, (second) effective size storage means 36, and (second) address comparison means 37 It is composed of

The PCI bridge 300 shown in FIG. 1 connects the primary PCI bus 100 and the secondary PCI bus 200.
The controller 12 of the first CPU (1) controls connection between the primary PCI bus 100, the processor 10, and the memory 11. The address comparing means 32 is a primary PCI bus 1
Compare the address on 00. Address conversion means 34
Converts the address of the primary PCI bus 100 to the address of the secondary PCI bus 200. The address comparing unit 37 compares whether the address accessed from the secondary PCI bus 200 is within the range from the base address storing unit 35 for the secondary PCI bus 200 to the effective size storing unit 36.

FIG. 2 shows an example of the configuration of the address translation mechanism of the PCI bridge 300 shown in FIG. 1, that is, the (primary) PC
Base address storage means 30 for I bus 100, effective size storage means 31 from this base address, (secondary) P
A conversion destination base address storage means 33 for the CI bus 200,
The detailed configuration of the address comparing means 32 and the address converting means 34 is shown. In FIG. 2, the (primary) PCI bus 10
The base address storage means 30 for 0, the effective size storage means 31 based on the base address, and the conversion destination base address storage means 33 for the (secondary) PCI bus 200 are composed of a plurality of entries (or a single entry). Address and size are specified. The address comparing means 32 searches each entry to determine whether the address on the primary PCI bus 100 matches the size of the effective size storing means 31 from the base address of the base address storing means 30 for the PCI bus 100. I do. When the result of the comparison by the address comparing means 32 matches, the address converting means 34 calculates a difference between the address on the PCI bus 100 and the base address of the base address storing means 30 for the PCI bus 100. And this difference is
It adds to the conversion destination base address of the conversion destination base address storage means 33 for the I bus 200, and
Find the address of

Next, the first of the PCI bridges according to the present invention will be described.
An address mapping operation according to the embodiment will be described with reference to FIGS. FIG. 3 is a PCI address mapping example of the PCI bridge 300 shown in FIG. Primary PC
The memory space of the I bus 100 includes the memory space of the first CPU (1) in “address = 0” to “address = A−1”.
“Address = A” to “address = B−1” indicates the memory space of the I / O card 13, and “Address = B” to “address = C−1” indicates the memory space of the I / O card 14. = C ”to“ address = TOP ”for PCI bridge 3
00 memory spaces are allocated. The memory space of the secondary PCI bus 200 is such that the memory space of the I / O card 24 is “address = D” to “address = E−1”, and the I / O card is “address = E” to “address = TOP”. 2
Allocate 3 memory spaces. Note that “address = 0” to
“Address = D−1” corresponds to the first PCI bus 100
It corresponds to the memory space of the CPU (1). “Address = D” means “address = A” to “address = TOP”
Are mapped within the range.

FIG. 4 shows the PCI bridge 30 shown in FIG.
0, an operation example of the first CPU (1) and the PCI bus 200 will be described. The first CPU (1) sets “address = C” to PCI
Entry 0 of base address storage means 30 for bus 100
(Step A1). “Size = 64” is set in the entry 0 of the effective size storage unit 31 (Step A)
2). “Address = D + 16” is set in the entry 0 of the conversion destination base address storage means 33 for the PCI bus 200 (step A3). Similarly, the first CPU (1) sets “address = C + 64” in the entry 1 of the base address storage unit 30 for the PCI bus 100 (step A).
4). “Size = 64” is set in the entry 1 of the effective size storage unit 31 (step A5). Further, "address = E" is set in the entry 1 of the conversion destination base address storage means 33 for the PCI bus 200 (step A6).

In these settings, the first CPU (1)
When reading the data of “address = E + 32” of the I / O card 23 from the I / O card 23, a read request is issued to the PCI bus 100 with “address = C + 96” (step A).
7). The PCI bridge 300 sets “address = C + 9
6 "is the base address storage means 3 for the PCI bus 100
The address comparing unit 32 detects that the address matches 0 with the range of “address = C + 64” to “size = 64” set in the entry 1 of the effective size storage unit 31 (step A7). The address conversion means 34 is a PCI bus 100
"Difference = C + 96-C + 64 = 32" is obtained from the entry 1 of the base address storage means 30 for the PCI bus 20.
"Address = E + 32" by adding to "Address = E" of entry 1 of conversion destination base address storage means 33 for 0
Issues a data read request to the secondary PCI bus 200. The I / O card 23 returns the corresponding data in response to "address = E + 32" (step A8).

When writing data from the first CPU (1) to “address = D + 48” of the I / O card 24, a write request is issued to the PCI bus 100 at “address = C + 32”. In the PCI bridge 300, “address = C + 32” matches the range of “address = C” to “size = 64” set in the entry 0 of the base address storage unit 30 for the PCI bus 100 and the effective size storage unit 31. This is detected by the address comparing means 32. The address conversion unit 34 calculates “difference = C +” from the entry 0 of the base address storage unit 30 for the PCI bus 100.
32-C = 32 ", and the" address = "of the entry 1 of the conversion destination base address storage means 33 for the PCI bus 200 is obtained.
D + 16 ", and issues a data write request to the secondary PCI bus 200 at" address = D + 48 ". I /
The O card 24 writes the corresponding data in response to "address = D + 48" (step A9).

When accessing the first CPU (1) from the I / O card 24, the first CPU (1) previously sets "address = 0" in the base address storage means 35 for the PCI bus 200 (step A10). ), “Size = A” is set in the effective size storage unit 36. When a data write request is issued from the I / O card 24 to the PCI bus 200 at “address = 8”, the PCI bridge 300
“Address = 8” is the entry 0 of the base address storage unit 35 for the PCI bus 200 and the effective size storage unit 36
The address comparison means 37 detects that the address matches the range of “address = 0” to “size = A” (step A11). If they match, "address = 8"
Issues a data write request to the primary PCI bus 100,
The first CPU (1) responds and stores the corresponding data in the memory 11
(Step A12). As a result, the maximum PCI address space can be secured for each PCI bus and
Even if mapping is performed by using the maximum address space of the buses 100 and 200, the entire address space of each PCI bus can be accessed. Therefore, the effect is obtained that the address space can be used to the maximum for each PCI bus.

FIG. 5 shows the configuration of a second embodiment of the PCI bridge according to the present invention. Since the basic configuration of the second embodiment is the same as that of the first embodiment shown in FIG. 1 described above, the same reference numerals are used for the corresponding components. Further, the following description will mainly be made on differences from the first embodiment. The primary PCI bus 100, the first CPU (1) connected thereto, and the I / O cards 13 and 14 are the same as in the first embodiment in FIG. However, the PCI bridge 300A includes the (primary) PCI bus 100 base address storage means 30, (first) effective size storage means 31, (first) address comparison means 32, (2)
(Next) PCI bus 200 conversion destination base address storage means 33, (first) address conversion means 34, (secondary) PCI
Base address storage means 35 for bus 200, (second) effective size storage means 36, and (second) address comparison means 37
In addition, a (primary) PCI bus 100 conversion destination base address storage means 38 and a (second) address conversion means 39 are provided. The components connected to the secondary PCI bus 200 include a second CPU (2) including a processor 20, a memory 21, and a controller 22, in addition to the I / O cards 23 and 24 in FIG. That is, the transmission path from the secondary PCI bus 200 to the primary PCI bus 100
A conversion destination base address storage means for CI bus 100 and an address conversion means 39 are provided.
The address conversion is performed even when the primary PCI bus 100 is accessed from 0.

Next, FIG. 6 shows a detailed configuration of the address translation mechanism in the second embodiment according to the present invention shown in FIG. The address translation mechanism of FIG.
A base address storage unit 35, an effective size storage unit 36 from the base address, a primary PCI bus conversion destination base address storage unit 38, an address comparison unit 37, and an address conversion unit 39. This configuration includes a base address storage unit 30 for the (primary) PCI bus 100 in FIG. 2, an effective size storage unit 31 from the base address, a secondary PCI bus conversion destination base address storage unit 33, an address comparison unit 32, This is the same as the address conversion means 34.

The PCI address mapping of the PCI bridge according to the second embodiment of the present invention shown in FIG. 5 will be described with reference to FIG. The memory space of the primary PCI bus 100 has the first address “address = 0” to “address = A−1”.
The memory space of the PU (1) is changed from “address = A” to “address = B−1” to the memory space of the I / O card 13,
The memory space of the I / O card 14 is allocated to “address = B” to “address = C−1”, and the memory space of the PCI bridge 300 is allocated to “address = C” to “address = TOP”. On the other hand, the memory space of the secondary PCI bus 200 is
“Address = 0” to “address = D−1” represent the memory space of the PCI bridge 300, “Address = D” to “address = E−1” represent the memory space of the I / O card 24,
The memory space of the I / O card 23 is changed from "address = F" to "address = F-1" to "address = F-1".
The memory space of the second CPU (2) is allocated to “TOP”.

Next, FIG. 8 shows the P according to the present invention shown in FIG.
The operation of the CI bridge 300A, the first CPU (1), and the PCI bus 200 will be described. The first CPU (1) sets “address = C” in entry 0 of the base address storage means 30 for the PCI bus 100 (step B1). “Size = 64” is set in the entry 0 of the effective size storage unit 31 (step B2). “Address = D” is set in entry 0 of the conversion destination base address storage means 33 for the PCI bus 200 (step B3). Similarly, the first CPU
(1) sets “address = 16” in the entry 1 of the base address storage means 35 for the PCI bus 200 (step B4). "Size = A-16" is set in the entry 1 of the effective size storage means 36 (step B5). Then, "address = 0" is set in the entry 1 of the conversion destination base address storage means 38 for the PCI bus 100 (step B6).

In the above setting, when data is written from the first CPU (1) to “address = D + 32” of the I / O card 24, a write request is issued to the primary PCI bus 100 at “address = C + 32”. I do. In the PCI bridge 300A, “address = C + 32” is set to “address = C” set in the entry 0 of the base address storage unit 30 for the PCI bus 100 and the effective size storage unit 31.
The address comparison unit 32 detects that the size matches the range of “size = 64”. The address conversion means 34 is a PC
From the entry 0 of the base address storage unit 30 for the I bus 100, “difference = C + 32−C = 32” is obtained, and added to the “address = D” of the entry 1 of the conversion destination base address storage unit 33 for the PCI bus 200, "Address = D +
At 32, a data write request is issued to the secondary PCI bus 200. The I / O card 24 writes the corresponding data in response to "address = D + 32" (step B7).

Similarly, from the I / O card 24 to the first CPU
When data is written to (1) at “address = 8”, a write request is issued to the secondary PCI bus 200 at “address = 24”. The PCI bridge 300A sets the “address = 24” in the range of “address = 16” to “size = A−16” set in the entry 1 of the base address storage unit 35 for the PCI bus 200 and the effective size storage unit 36. The coincidence is detected by the address comparing means 37. The address conversion means 39 calculates “difference = 24” from the entry 1 of the base address storage means 35 for the PCI bus 200.
−16 = 8 ”, and the“ address = 0 ”of the entry 1 of the conversion destination base address storage means 38 for the PCI bus 100
To the primary PCI bus 100 at “address = 8”.
Issue a data write request, and the CPU (1) responds and writes the corresponding data to the memory 11 (step B).
8).

The configuration and operation of the preferred embodiment of the PCI bridge according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0027]

As described above, according to the PCI bridge of the present invention, by providing the address translation mechanism,
This has a practically remarkable effect that a system capable of maximizing the use of the address space of each PCI bus becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a PCI bridge according to the present invention.

FIG. 2 is a detailed diagram showing a configuration of an address translation mechanism of the PCI bridge according to the present invention shown in FIG. 1;

FIG. 3 is a diagram showing a PCI address mapping example of the PCI bridge shown in FIG. 1;

FIG. 4 is a flowchart showing an operation of the PCI bridge shown in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a second embodiment of a PCI bridge according to the present invention.

FIG. 6 is a diagram showing a detailed configuration of an address translation mechanism in the second embodiment shown in FIG.

FIG. 7 is a diagram illustrating an example of PCI address mapping in the PCI bridge illustrated in FIG. 5;

8 is a flowchart showing an operation of the PCI bridge shown in FIG.

FIG. 9 is a diagram showing a configuration of a conventional PCI bridge.

FIG. 10 is a diagram showing an example of a PCI address mapping of the conventional PCI bridge shown in FIG. 9;

FIG. 11 is a flowchart illustrating the operation of the conventional PCI bridge shown in FIG.

[Explanation of symbols]

Reference Signs List 100 primary (first) PCI bus 200 secondary (second) PCI bus 13, 14, 23, 24 I / O card 300, 300A PCI bridge 30 (primary) PCI bus base address storage means 31 (first) ) Effective size storage means 32 (first) address comparison means 33 (secondary) conversion destination base address storage means for PCI bus 200 34 (first) one address conversion means 35 (secondary) base address storage means for PCI bus 200 36 (second) effective size storage means 37 (second) address comparison means 38 (primary) conversion destination base address storage means for PCI bus 100 39 (second) address conversion means

Claims (6)

[Claims] A first PCI bus base address storage means connected to a first PCI bus and a second PCI bus for storing a base address of the first PCI bus;
The first effective size storage means for storing the effective size from the base address indicated by the CI bus base address storage means and the PCI address determined on the first PCI bus are determined from the base address indicated by the first PCI bus base address storage means. In a PCI bridge including first address comparing means for comparing and judging whether or not the size is within an effective size indicated by the first effective size storing means, storing a second PCI bus conversion destination base address for storing the second PCI bus conversion destination base address Means for converting the second PCI bus based on the output of the second PCI bus conversion destination base address storing means and the first address comparing means.
A PCI bridge, comprising: first address conversion means for obtaining an I bus address. 2. The method according to claim 1, wherein the first address conversion means is configured to output the first address when the comparison result of the first address comparison means matches.
A difference between the address on the PCI bus and the base address of the first PCI bus base address storage means is obtained, and the difference is added to the conversion destination base address of the second PCI bus conversion destination base address storage means to obtain the address of the second PCI bus. 2. The PCI according to claim 1, wherein the value is obtained.
bridge. 3. A plurality of I / O cards are connected to the second PCI bus, and a memory space of the first PCI bus allocated to a PCI bridge is allocated to the plurality of I / O cards by the first address conversion means. The PCI bridge according to claim 1, wherein a memory space of the second PCI bus is allocated to the PCI bridge. 4. A second PCI bus base address storage means for storing the second PCI bus base address; a second effective size storage means for storing an effective size; a second PCI bus base address storage means; 2
2. The PCI bridge according to claim 1, further comprising second address comparing means for comparing addresses based on effective size storage means. 5. A second address conversion means for receiving a coincidence output from said second address comparison means and converting the same to an address for said first PCI bus, and providing said second address conversion means with a first P address.
First PCI for outputting CI bus conversion destination base address
5. The PCI bridge according to claim 4, further comprising a bus conversion destination base address storage unit. 6. The first and second address translation means,
The PCI bridge according to claim 5, wherein the PCI bridge is connected to the second PCI bus and the first PCI bus, respectively.