JPS55113183A - Address converter - Google Patents

Address converter

Info

Publication number
JPS55113183A
JPS55113183A JP2042979A JP2042979A JPS55113183A JP S55113183 A JPS55113183 A JP S55113183A JP 2042979 A JP2042979 A JP 2042979A JP 2042979 A JP2042979 A JP 2042979A JP S55113183 A JPS55113183 A JP S55113183A
Authority
JP
Japan
Prior art keywords
addresses
blocks
memory
adder
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2042979A
Other languages
Japanese (ja)
Inventor
Takenori Makino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2042979A priority Critical patent/JPS55113183A/en
Publication of JPS55113183A publication Critical patent/JPS55113183A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make it possible to convert a sufficiently-large logical address into a physical address and also to enable high speed retrieval by controlling a conversion table in the format of multiple page indexes.
CONSTITUTION: An information processing system consists of processor 1, memory 2 stored with a multiple page tree maintaining a conversion table of logical addresses and physical addresses, and retrieval unit 3. Then, processor 1 sends logical addresses to be converted, e.g., three blocks B1, B2 and B3 to selector circuit 5 by way of register 4. Circuit 5 sends blocks B1 and B2 to associative memory 6 and B3 to adder 7. Memory 6 checks whether sent blocks exist or not and when so, corresponding physical addresses are added by adder 7 to store the sum in register 9. When not, a command is sent to selector circuit 5 to repeat selecting operation. Thus, a great quantity of addresses can be converted and high-speed retrieval can be attained.
COPYRIGHT: (C)1980,JPO&Japio
JP2042979A 1979-02-22 1979-02-22 Address converter Pending JPS55113183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2042979A JPS55113183A (en) 1979-02-22 1979-02-22 Address converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2042979A JPS55113183A (en) 1979-02-22 1979-02-22 Address converter

Publications (1)

Publication Number Publication Date
JPS55113183A true JPS55113183A (en) 1980-09-01

Family

ID=12026788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2042979A Pending JPS55113183A (en) 1979-02-22 1979-02-22 Address converter

Country Status (1)

Country Link
JP (1) JPS55113183A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837884A (en) * 1981-08-28 1983-03-05 Nec Corp Address converting system
US7492660B2 (en) * 1989-04-13 2009-02-17 Sandisk Corporation Flash EEprom system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837884A (en) * 1981-08-28 1983-03-05 Nec Corp Address converting system
US7492660B2 (en) * 1989-04-13 2009-02-17 Sandisk Corporation Flash EEprom system

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