JPS5779743A - Synchronizing shape circuit - Google Patents

Synchronizing shape circuit

Info

Publication number
JPS5779743A
JPS5779743A JP55155690A JP15569080A JPS5779743A JP S5779743 A JPS5779743 A JP S5779743A JP 55155690 A JP55155690 A JP 55155690A JP 15569080 A JP15569080 A JP 15569080A JP S5779743 A JPS5779743 A JP S5779743A
Authority
JP
Japan
Prior art keywords
circuit
gate
output
synchronizing signal
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155690A
Other languages
English (en)
Inventor
Toshio Komori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON MARANTZ KK
Marantz Japan Inc
Original Assignee
NIPPON MARANTZ KK
Marantz Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON MARANTZ KK, Marantz Japan Inc filed Critical NIPPON MARANTZ KK
Priority to JP55155690A priority Critical patent/JPS5779743A/ja
Publication of JPS5779743A publication Critical patent/JPS5779743A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP55155690A 1980-11-05 1980-11-05 Synchronizing shape circuit Pending JPS5779743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155690A JPS5779743A (en) 1980-11-05 1980-11-05 Synchronizing shape circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155690A JPS5779743A (en) 1980-11-05 1980-11-05 Synchronizing shape circuit

Publications (1)

Publication Number Publication Date
JPS5779743A true JPS5779743A (en) 1982-05-19

Family

ID=15611409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155690A Pending JPS5779743A (en) 1980-11-05 1980-11-05 Synchronizing shape circuit

Country Status (1)

Country Link
JP (1) JPS5779743A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224631A (ja) * 1985-03-29 1986-10-06 Mitsubishi Electric Corp 信号伝達系の外乱防止回路
JPS6342522A (ja) * 1986-08-08 1988-02-23 Matsushita Electric Ind Co Ltd 位相同期ル−プ回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224631A (ja) * 1985-03-29 1986-10-06 Mitsubishi Electric Corp 信号伝達系の外乱防止回路
JPH0586691B2 (ja) * 1985-03-29 1993-12-14 Mitsubishi Electric Corp
JPS6342522A (ja) * 1986-08-08 1988-02-23 Matsushita Electric Ind Co Ltd 位相同期ル−プ回路

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