JPS5778144A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5778144A
JPS5778144A JP55153887A JP15388780A JPS5778144A JP S5778144 A JPS5778144 A JP S5778144A JP 55153887 A JP55153887 A JP 55153887A JP 15388780 A JP15388780 A JP 15388780A JP S5778144 A JPS5778144 A JP S5778144A
Authority
JP
Japan
Prior art keywords
electrode
substrate
solder
solder material
low temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153887A
Other languages
Japanese (ja)
Inventor
Kenichi Kizawa
Noboru Baba
Hiroshi Soeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55153887A priority Critical patent/JPS5778144A/en
Publication of JPS5778144A publication Critical patent/JPS5778144A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H01L23/4928—Bases or plates or solder therefor characterised by the materials the materials containing carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To form a bonding structure of a semiconductor device having rigidity at low temperature and good electric characteristics by providing the prescribed solder materials for a semiconductor substrate and a supporting electrode and disposing and bonding solder material made of Sn or In between the soldering materials. CONSTITUTION:A Cu (or Ni) solder material 12 is provided at an Mo supporting electrode 10 soldered, for example, to a copper electrode 5, for example, in a flat diode 1, and Sn (or In) solder material 13 is interposed and bonded between the solder material 12 and a solder 11 made of, for example, aluminum (or any of Au, Pt and Cr). An aluminum electrode 6 is provided on the upper surface of a substrate 9, and is contacted under pressure via a W buffer plate 16. Since this bonding structure can be rigidly bonded at a low temperature (approx. 300 deg.C), it can reduce the thermal stress to the substrate 9, and preferable electrically contacting property can be contained without the conductive type of the substrate 9. Various types of material such as composite material in which carbon fiber is buried in W, Mo, Fe, Cu, Al, Fe-Ni alloy, Cu matrix can be applied to the electrode 10.
JP55153887A 1980-11-04 1980-11-04 Semiconductor device Pending JPS5778144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153887A JPS5778144A (en) 1980-11-04 1980-11-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153887A JPS5778144A (en) 1980-11-04 1980-11-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5778144A true JPS5778144A (en) 1982-05-15

Family

ID=15572279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153887A Pending JPS5778144A (en) 1980-11-04 1980-11-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5778144A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638928A1 (en) * 1993-08-09 1995-02-15 Siemens Aktiengesellschaft Power semiconductor device with pressure contact
JP2008028295A (en) * 2006-07-25 2008-02-07 Toyota Central Res & Dev Lab Inc Power semiconductor module and production method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114176A (en) * 1974-02-16 1975-09-06
JPS52143763A (en) * 1976-05-26 1977-11-30 Hitachi Ltd Soldering method to holding substrate for semiconductor substrates
JPS546463A (en) * 1977-06-17 1979-01-18 Toshiba Corp Arranging method for semiconductor element
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114176A (en) * 1974-02-16 1975-09-06
JPS52143763A (en) * 1976-05-26 1977-11-30 Hitachi Ltd Soldering method to holding substrate for semiconductor substrates
JPS546463A (en) * 1977-06-17 1979-01-18 Toshiba Corp Arranging method for semiconductor element
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638928A1 (en) * 1993-08-09 1995-02-15 Siemens Aktiengesellschaft Power semiconductor device with pressure contact
JP2008028295A (en) * 2006-07-25 2008-02-07 Toyota Central Res & Dev Lab Inc Power semiconductor module and production method therefor

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