JPS5764921A - Manufacture of gaas integrated circuit - Google Patents

Manufacture of gaas integrated circuit

Info

Publication number
JPS5764921A
JPS5764921A JP55139773A JP13977380A JPS5764921A JP S5764921 A JPS5764921 A JP S5764921A JP 55139773 A JP55139773 A JP 55139773A JP 13977380 A JP13977380 A JP 13977380A JP S5764921 A JPS5764921 A JP S5764921A
Authority
JP
Japan
Prior art keywords
mark
alignment
sio2 film
annealing
carried out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55139773A
Other languages
Japanese (ja)
Other versions
JPH0140487B2 (en
Inventor
Yasuo Igawa
Nobuyuki Toyoda
Masao Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55139773A priority Critical patent/JPS5764921A/en
Publication of JPS5764921A publication Critical patent/JPS5764921A/en
Publication of JPH0140487B2 publication Critical patent/JPH0140487B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To facilitate alignment of a microscopic mask and improve the perform ance of a planar IC, by a method wherein an alignment mark is formed on a protecting film in the process for opening windows for selective ion injection, and after active layer are formed by injecting ions, with the mark left, the protecting film is removed, and the active layers are annealed. CONSTITUTION:For example, in the process for manufacturing an IC comprising a FET of planar structure, an SiO2 film is deposited on a semiinsulative substrate, and windows are opened in the SiO2 film in order to form active layers in source, drain and channel regions by injecting ions respectively. In this first window opening process, SiO2 film patterns 22 in the number corresponding to the number of photoprocesses carried out afterward are formed at a position separate from the element region. On the other hand, the mask used in the subsequent photoprocess is provided with an alignment mark 31 positioned inward a mark 23 in a transparent region 32, for example, thereby to perform alignment. The mark 23 is not removed but left even when annealing is carried out so as to be used for alignment in, e.g., a gate electrode forming process. Thereby, it becomes unnecessary to each the substrate in order to form a mark, and substantially a capless annealing can be per formed. Accordingly, the IC can be made more microcsopic and higher in performance.
JP55139773A 1980-10-08 1980-10-08 Manufacture of gaas integrated circuit Granted JPS5764921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55139773A JPS5764921A (en) 1980-10-08 1980-10-08 Manufacture of gaas integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55139773A JPS5764921A (en) 1980-10-08 1980-10-08 Manufacture of gaas integrated circuit

Publications (2)

Publication Number Publication Date
JPS5764921A true JPS5764921A (en) 1982-04-20
JPH0140487B2 JPH0140487B2 (en) 1989-08-29

Family

ID=15253070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55139773A Granted JPS5764921A (en) 1980-10-08 1980-10-08 Manufacture of gaas integrated circuit

Country Status (1)

Country Link
JP (1) JPS5764921A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5075772A (en) * 1973-11-07 1975-06-21
JPS51147179A (en) * 1975-06-12 1976-12-17 Fujitsu Ltd Method of munufacturing of semiconductor device
JPS52139374A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Alignment pattern forming method for mask alignment
JPS5341984A (en) * 1976-09-22 1978-04-15 Siemens Ag Method of positioning exposure mask

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5075772A (en) * 1973-11-07 1975-06-21
JPS51147179A (en) * 1975-06-12 1976-12-17 Fujitsu Ltd Method of munufacturing of semiconductor device
JPS52139374A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Alignment pattern forming method for mask alignment
JPS5341984A (en) * 1976-09-22 1978-04-15 Siemens Ag Method of positioning exposure mask

Also Published As

Publication number Publication date
JPH0140487B2 (en) 1989-08-29

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