JPS5764848A - Processor of pipeline control data - Google Patents

Processor of pipeline control data

Info

Publication number
JPS5764848A
JPS5764848A JP55139835A JP13983580A JPS5764848A JP S5764848 A JPS5764848 A JP S5764848A JP 55139835 A JP55139835 A JP 55139835A JP 13983580 A JP13983580 A JP 13983580A JP S5764848 A JPS5764848 A JP S5764848A
Authority
JP
Japan
Prior art keywords
operand
instruction
given
processor
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55139835A
Other languages
Japanese (ja)
Other versions
JPS6160458B2 (en
Inventor
Hidekazu Matsumoto
Tadaaki Bando
Hideo Maejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55139835A priority Critical patent/JPS5764848A/en
Priority to CA000377496A priority patent/CA1174370A/en
Priority to GB8114857A priority patent/GB2077965B/en
Priority to KR1019810001672A priority patent/KR850001015B1/en
Priority to DE3119741A priority patent/DE3119741C2/en
Priority to US06/265,168 priority patent/US4454578A/en
Publication of JPS5764848A publication Critical patent/JPS5764848A/en
Priority to US06/873,174 priority patent/USRE32493E/en
Publication of JPS6160458B2 publication Critical patent/JPS6160458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To realize the high-speed decoding of an instruction and to enhance the performance of a processor in case the final operand of the instruction is given in the register direct mode. CONSTITUTION:An IF unit 305, a data aligner 306 and an instruction decoding unit 309 are provided. For the process of two operand addition instruction, the contents are added between the 1st and 2nd operands, and the result of this addition is stored in the position of the 2nd operand. For a pattern which is read out of an ROM405 in an OP code of the addition instruction, the pattern of step 1 is given with the read as an access type AT of the 1st operand and with the word as a data type DT respectively. Then the BENDR/ is set since the 1st operand is identical with the operand preceding the final operand. For the pattern of step 2, the modify is given as the access type AT of an operand and the word is given as a data type DT respectively. And 1 is set to the END since the 2nd operand is identical with the final operand.
JP55139835A 1980-05-19 1980-10-08 Processor of pipeline control data Granted JPS5764848A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP55139835A JPS5764848A (en) 1980-10-08 1980-10-08 Processor of pipeline control data
CA000377496A CA1174370A (en) 1980-05-19 1981-05-13 Data processing unit with pipelined operands
GB8114857A GB2077965B (en) 1980-05-19 1981-05-14 Data processing unit with pipelined operands
KR1019810001672A KR850001015B1 (en) 1980-05-19 1981-05-15 Pipeline control data processing system between operands
DE3119741A DE3119741C2 (en) 1980-05-19 1981-05-18 Data processing unit
US06/265,168 US4454578A (en) 1980-05-19 1981-05-19 Data processing unit with pipelined operands
US06/873,174 USRE32493E (en) 1980-05-19 1986-06-11 Data processing unit with pipelined operands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55139835A JPS5764848A (en) 1980-10-08 1980-10-08 Processor of pipeline control data

Publications (2)

Publication Number Publication Date
JPS5764848A true JPS5764848A (en) 1982-04-20
JPS6160458B2 JPS6160458B2 (en) 1986-12-20

Family

ID=15254599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55139835A Granted JPS5764848A (en) 1980-05-19 1980-10-08 Processor of pipeline control data

Country Status (1)

Country Link
JP (1) JPS5764848A (en)

Also Published As

Publication number Publication date
JPS6160458B2 (en) 1986-12-20

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