JPS5760843A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5760843A
JPS5760843A JP13545680A JP13545680A JPS5760843A JP S5760843 A JPS5760843 A JP S5760843A JP 13545680 A JP13545680 A JP 13545680A JP 13545680 A JP13545680 A JP 13545680A JP S5760843 A JPS5760843 A JP S5760843A
Authority
JP
Japan
Prior art keywords
groove
mesa
chemical etching
layer
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13545680A
Other languages
Japanese (ja)
Inventor
Kazuko Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13545680A priority Critical patent/JPS5760843A/en
Publication of JPS5760843A publication Critical patent/JPS5760843A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To stabilize manufacture of a two-stage mesa structure and improve highvoltage endurance of an element, by providing a shallow and wide groove by chemical etching, forming a mesa groove across a junction in the groove with die, and etching the mesa groove. CONSTITUTION:A P-diffused layer 2 is formed on an N-substrate 1. An opening 5 is provided on an oxide film 4, which has a region to form a mesa groove, for an element whose construction is to select and diffuse an N-layer 3. A groove shallower by 5-10mum than a final one is formed in the opening 5 by chemical etching. Next, a groove 7 deeper than a junction 8 is formed by die with a blade of 100- 200mum wide. A damaged layer for cut-off is removed by 5-100mum of chemical etching. After a two-stage mesa construction 9 is completed, an element of high- voltage endurance is made through such processes as glass passivation, electron formation, pellet division, and the like. Consequently, a two-stage mesa structure is manufactured stably in desirable dimension. A yield is improved for high-voltage endurance.
JP13545680A 1980-09-29 1980-09-29 Manufacture of semiconductor device Pending JPS5760843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13545680A JPS5760843A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13545680A JPS5760843A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5760843A true JPS5760843A (en) 1982-04-13

Family

ID=15152128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13545680A Pending JPS5760843A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5760843A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858808A (en) * 1996-01-16 1999-01-12 Deutsche Itt Industries Gmbh Process and auxiliary device for fabricating semiconductor devices
EP4068338A1 (en) * 2021-03-29 2022-10-05 Littelfuse Semiconductor (Wuxi) Co., Ltd. Semiconductor mesa device formation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858808A (en) * 1996-01-16 1999-01-12 Deutsche Itt Industries Gmbh Process and auxiliary device for fabricating semiconductor devices
EP4068338A1 (en) * 2021-03-29 2022-10-05 Littelfuse Semiconductor (Wuxi) Co., Ltd. Semiconductor mesa device formation method

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