JPS5760750A - Input and output supervisory system - Google Patents

Input and output supervisory system

Info

Publication number
JPS5760750A
JPS5760750A JP13559680A JP13559680A JPS5760750A JP S5760750 A JPS5760750 A JP S5760750A JP 13559680 A JP13559680 A JP 13559680A JP 13559680 A JP13559680 A JP 13559680A JP S5760750 A JPS5760750 A JP S5760750A
Authority
JP
Japan
Prior art keywords
circuit
input signals
input
output
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13559680A
Other languages
Japanese (ja)
Other versions
JPS6340380B2 (en
Inventor
Takeo Fukushima
Tetsuo Murase
Takashi Wakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13559680A priority Critical patent/JPS5760750A/en
Publication of JPS5760750A publication Critical patent/JPS5760750A/en
Publication of JPS6340380B2 publication Critical patent/JPS6340380B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To supervise inputs and outputs easily, by using a phase difference to check multiplexing or demultiplexing of the input signal inputted to a transmission device by adding a memory circuit to an input and output supervisory device. CONSTITUTION:Input signals A-C are inputted to a transmission device 1, and a multiplexed (or demultiplexed) signal is outputted from the device 1 to an output terminal 3. Meanwhile, input signals A-C are inputted to a selecting circuit 8 of an input and output supervisory device 11, and phases corresponding to input signals A-C are read out into a memory circuit 10 by the output of the circuit 8, and their phase difference is set to a phase correcting circuit 9. Phases of input signals A-C are corrected by the circuit 9, and phase corrected input signals and output signals corresponding to input signals A-C from the device 1 are compared with each other in phase by a phase comparing circuit 6 to check whether input signals A-C are multiplexed correctly or not; and if they are multiplexed correctly, OK is displayed on a display circuit 7.
JP13559680A 1980-09-29 1980-09-29 Input and output supervisory system Granted JPS5760750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13559680A JPS5760750A (en) 1980-09-29 1980-09-29 Input and output supervisory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13559680A JPS5760750A (en) 1980-09-29 1980-09-29 Input and output supervisory system

Publications (2)

Publication Number Publication Date
JPS5760750A true JPS5760750A (en) 1982-04-12
JPS6340380B2 JPS6340380B2 (en) 1988-08-10

Family

ID=15155510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13559680A Granted JPS5760750A (en) 1980-09-29 1980-09-29 Input and output supervisory system

Country Status (1)

Country Link
JP (1) JPS5760750A (en)

Also Published As

Publication number Publication date
JPS6340380B2 (en) 1988-08-10

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