JPS55109051A - Monitor system - Google Patents

Monitor system

Info

Publication number
JPS55109051A
JPS55109051A JP1704679A JP1704679A JPS55109051A JP S55109051 A JPS55109051 A JP S55109051A JP 1704679 A JP1704679 A JP 1704679A JP 1704679 A JP1704679 A JP 1704679A JP S55109051 A JPS55109051 A JP S55109051A
Authority
JP
Japan
Prior art keywords
units
output
multiplying
same structure
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1704679A
Other languages
Japanese (ja)
Inventor
Masaaki Ogiso
Nobuhisa Kamoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1704679A priority Critical patent/JPS55109051A/en
Publication of JPS55109051A publication Critical patent/JPS55109051A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Abstract

PURPOSE:To secure the monitor for the multiplying unit by giving the comparison to the output of the multiplying units of the same structure in case the PCM signal is multiplied. CONSTITUTION:The multiplication is given through multiplying unit 1 plus unit 6 of the same structure to each PCM signal of input channels CH1-CHn. The both multiplication output are then supplied to comparison circuit 7 to be compared with every bit. If both the multiplying units are normal, their output are identical to each other. And thus no disagreement output is produced from circuit 7; while the disagreement output is produced if either one of the units has some fault. In this connection, two units of the multiplying unit featuring the same structure are used. As a result, the correction can be omitted for the delay time of both units, thus simplifying the circuit constitution.
JP1704679A 1979-02-16 1979-02-16 Monitor system Pending JPS55109051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1704679A JPS55109051A (en) 1979-02-16 1979-02-16 Monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1704679A JPS55109051A (en) 1979-02-16 1979-02-16 Monitor system

Publications (1)

Publication Number Publication Date
JPS55109051A true JPS55109051A (en) 1980-08-21

Family

ID=11933043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1704679A Pending JPS55109051A (en) 1979-02-16 1979-02-16 Monitor system

Country Status (1)

Country Link
JP (1) JPS55109051A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59122038A (en) * 1982-12-16 1984-07-14 Fujitsu Ltd On-line monitoring system of pcm multiplexer
JPS6392215A (en) * 1986-10-03 1988-04-22 富士電機株式会社 Abnormality indication system in digital protective relay

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59122038A (en) * 1982-12-16 1984-07-14 Fujitsu Ltd On-line monitoring system of pcm multiplexer
JPS6392215A (en) * 1986-10-03 1988-04-22 富士電機株式会社 Abnormality indication system in digital protective relay

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