JPS5775045A - Input and output monitor system - Google Patents

Input and output monitor system

Info

Publication number
JPS5775045A
JPS5775045A JP15155980A JP15155980A JPS5775045A JP S5775045 A JPS5775045 A JP S5775045A JP 15155980 A JP15155980 A JP 15155980A JP 15155980 A JP15155980 A JP 15155980A JP S5775045 A JPS5775045 A JP S5775045A
Authority
JP
Japan
Prior art keywords
circuit
channel
output
detected
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15155980A
Other languages
Japanese (ja)
Inventor
Takeo Fukushima
Takashi Wakabayashi
Tetsuo Murase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15155980A priority Critical patent/JPS5775045A/en
Publication of JPS5775045A publication Critical patent/JPS5775045A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make the operation speed high and simplify the circuit constitution, by measuring the phase difference between input and output signals and by using this phase difference to compare input and output signals. CONSTITUTION:Input digital signals of a lower group are multiplexed by a multiple converting device 3 and are transmitted to a transmission line 10 through an output terminal 2. Meanwhile, the phase difference between the frame pattern of a pertinent channel, for example, a channel CH1 detected by a frame pattern detecting circuit 17 and that detected by a frame pattern detecting circuit 16 is detected as the count number of clocks by a counter 21 and is held in a latch circuit 22. By this phase difference, a bit of the channel CH1 corresponding to a channel CH1' is detected by a selector 15 and is inputted to a comparing circuit 19. The output digital signal of the channel CH1' is selected by a selecting circuit 18, and the output is inputted to the comparing circuit 19 and is compared, and if they coincide with each other, an alarm circuit 24 is driven by the output of the comparing circuit 19.
JP15155980A 1980-10-29 1980-10-29 Input and output monitor system Pending JPS5775045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15155980A JPS5775045A (en) 1980-10-29 1980-10-29 Input and output monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15155980A JPS5775045A (en) 1980-10-29 1980-10-29 Input and output monitor system

Publications (1)

Publication Number Publication Date
JPS5775045A true JPS5775045A (en) 1982-05-11

Family

ID=15521165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15155980A Pending JPS5775045A (en) 1980-10-29 1980-10-29 Input and output monitor system

Country Status (1)

Country Link
JP (1) JPS5775045A (en)

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