KR850001204B1 - Indicator - Google Patents

Abstract

An indicating circuit uses a time-division transmission circuit instead of a diode matrix circuit to display the floor numbers for an elevator. The transmitting element (A) comprises an input of floor number signals (1), a binary signal converter (6) that converts the floor number signals to binary signals, and a time-division transmission circuit (7) that transmits the segment signals and synchronizing signals. A receiving element (B) comprises a synchronizing signal detector (9), a sampling circuit (10), a data ratch circuit (11) and a digital LED indicator (5).

Description

Floor water check circuit for monitoring panel of elevator

1 is a conventional circuit diagram.

2 is a block diagram of the present invention.

3 is a detailed circuit diagram of the transmitter of the present invention.

4 is a truth table of the binary decoder B in the present invention.

5 is the truth table of the seven-segment decoder (c) in the present invention.

6 (a) is a truth table of the decade counter T ₃ in the present invention.

6 (b) is a waveform diagram of each part of the decade counter T ₃ in the present invention.

7 is a dermal pitch table of the multiplexer (M) in the present invention.

8 is a waveform diagram of each part of the time division transfer circuit section in the present invention.

9 is a detailed circuit diagram of the receiver (b) of the present invention.

10 is a waveform diagram of each part of the receiver (b) in the present invention.

11 is a truth table of the binary counter T ₁ (T ₂ ) (T ₄ ) (T ₅ ) (T ₆ ) in the present invention.

12 is a truth table of the demultiplexer (DM) in the present invention.

13 is a truth table of data latches DR ₁ -DR ₇ in the present invention.

* Explanation of symbols for main parts of the drawings

A: transmitter B: receiver

A: floor signal input part b: diode matrix circuit part

S: Segment Decoder

ㄹ: LED driver ㅁ: Digital LED Indicator

ㅂ: binary signal converter ㅅ: time division transmission circuit

ㅇ: Pulse generator 동기: Synchronous signal detector

J: sampling circuit part j: data latch circuit part

A ₁ -A ₈ : Question B: Binary Decoder

D _a -D _g : Each segment of the LED DR ₁ -DR ₇ : Data Latch

DM: Demultiplexer

I ₁ -I ₅ , I ₁₀ -I ₁₁ : Inverter I ₆ -I ₉ : Inverter Buffer

M: Multiplexer OR _1- OR ₄ : ORGATE

T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ : Binary counter

T ₃ : Decade Counter

The present invention relates to a monitoring response floor number display circuit of an elevator using a time division transmission method.

Conventionally, as shown in FIG. 1, a floor signal is converted into a binary signal through a diode matrix circuit (L), and transmitted to a monitor panel. A parallel binary signal is transmitted from a 7-segment decoder (C) at a receiving panel. It converts into 7-segment signal and amplifies this signal in LED driver (ㄹ) to drive LED (ㅁ) of digital indicator. Therefore, it requires 4 signal transmission lines to display 1 digit and diode matrix circuit (L). There is a problem that the process is very difficult because the circuit configuration is complicated by use.

The present invention converts a floor signal of an elevator into a binary signal and converts it into a 7-segment signal in order to solve the conventional problems, and sequentially transmits the low and high signals of each segment to one transmission line, and transmits the signal from a receiving station. In order to drive the LEDs of the digital indicator by sequentially receiving each input signal to be input, which will be described in detail by the accompanying drawings as follows.

As shown in FIG. 2, a binary signal converting unit for decoding a floor signal as a binary signal is connected to a floor signal input unit a composed of a movable contact group F1 and a fixed contact group S ₁ -S ₉ . A 7-segment decoder (c) for decoding the binary signal into the 7-segment signal of the LED and connecting the 7-segment decoder (c) to the 7-segment decoder (c). The signal is sequentially transmitted along with the synchronization signal, and a time division transmission circuit portion (S) to which a pulse generator (O) is connected is connected to constitute a transmitter (A).

In addition, a synchronization signal detection unit (L) for receiving a signal transmitted from the time division transmission circuit unit (S) of the transmitter (D) and detecting a synchronization signal is connected, and is operated from the synchronization signal detection unit to the synchronization signal detection unit (P). ㅇ ') is connected to the sampling circuit unit (z) connected, and the data latch circuit unit (L) to sequentially latch the data according to the clock generated from the sampling circuit unit (Z) to the sampling circuit unit (Z), The output terminal of the data latch circuit section (k) is connected to the digital LED indicator (wh) to constitute a receiving section (b). Reference symbol B ⁺ is a power supply terminal.

Referring to the effects of the present invention configured as described above are as follows.

3 is a detailed circuit diagram of the transmitter of the present invention. For example, assuming that the elevator is located on the third floor, the movable contact Fg is in contact with the fixed contact S ₃ , and the power source B ⁺ is a resistor R. FIG. ₃ ) The signal is applied to the input terminal I ₃ of the binary decoder B through the input terminal I ₃ , so that a high signal appears at the input terminal I ₃ , and the output terminal Q ₀ (Q ₁ ) (Q ₂ ) As shown in the truth table shown in FIG. 4, high (H), high (H), and low (L) signals appear respectively.

The high (H), high (H) and low (L) signals are input to the input terminals A, B, and C of the 7-segment decoder C, and the fixed contacts S ₈ , A low (L) signal is input to another input terminal (D) through the resistor (R ₈ ) and the or gate (OR ₂ ), so the output terminal (a) (b) (c) of the 7 segment decoder (c) is provided. (d) (e) (f) (g) include high (H), high (H), high (H), high (H), low (L), low (L), as shown in FIG. The high signal will appear.

On the other hand, the binary counter (T ₁ ) is divided into 16 divisions of the clock pulse of the pulse generator (in this case, the output terminals (Q ₀ ), (Q ₁ ), (Q ₂ ), and (Q ₃ ) of the binary counter (T ₁ ). ), the input terminal (CL) the clock pulses Sikkim respectively 2, 4, 8, 16, frequency divider to output a) to the binary counter (output terminal (Q ₀₎ of the counter (T ₂₎ thereby the binary input to the T _2), In Q ₁ , Q ₂ , and Q ₃ , one count is made every 16 clocks of the pulse generator (O), so as shown in FIG. 11, low (L), low (L), low (L), From low (L) and signal state to high (H), high (H), high (H), high (H) signal state changes.

The output signal of the binary counter T ₂ thus changed is applied to the input terminals A '(B') (C ') (D') of the multiplexer M, so that the binary counter T ₂ Output (Q ₀ ) (Q ₁ ) (Q ₂ ) (Q ₃ ) signals are high (H) and high (H) while low (L), low (L), low (L), and low (L) states In order to sequentially change the high (H) and high (H) states, the output terminal (Zo) of the multiplexer (M) has a multiplexer as shown in the truth table shown in FIG. 7 every 16 clocks of the pulse generator (O). M) input terminals (D ₀ ), (D ₁ ). … It is shown at (D ₁₅ ).

At this time, in the decade counter T ₃ , which is operated as shown in FIG. 6 (a), the clock terminal of the pulse generator O is divided by 4 at the binary counter T ₁ , and its output terminal ( Q ₁ ) Since the signal is applied, as shown in FIG. 6 (b), the output waveforms of the decade counter T ₃ are the output terminals Q ₀ , Q ₁ , Q ₂ , Q ₃ , and Q ₃ . Q ₄₎ in order of high (H) signal is sequentially displayed, so the terminal moment the signal that appears on his terminal (Q ₄₎ which is in a high state (Q ₄₎ and the signal is high appears on gongjeop a reset terminal (R) of The decay counter (T ₃ ) is reset so that the high signal is repeated to the output terminals (Q ₀ ), (Q ₁ ), (Q ₂ ), (Q ₃ ), and (Q ₄ ). It will appear sequentially.

Therefore, the signal waveform appearing at the three input terminals of the cucumber gate OR ₃ is displayed as shown in (h) of FIG. 6 (b).

On the other hand, the signal appearing at the output terminals (a) (b) (c) (d) (g) of the 7-segment decoder (c) becomes a high state, and the gate (A ₁ ), (A ₂ ), (A ₃₎ ), (A ₄ ) and (A ₇ ) on one side of the input terminal and the other gates of the end gates (A ₁ ), (A ₂ ), (A ₃ ), (A ₄ ), (A ₇ ) Since the output terminal signal of (OR ₃ ) is applied, only the terminals D ₂ , (D ₃ ), (D ₄ ), (D ₅ ), and (D ₈ ) among the input terminals of the multiplexer (M) The output signal of ₃ ) is input.

Here, the power supply B ⁺ is applied to the input terminal D ₀ , and the output terminal signal of the OR gate OR ₃ is applied to the input terminal D ₁ , so that the output terminal Zo of the multiplexer M is applied to the input terminal D ₁ . The signal waveform as shown in FIG. 8 (a) appears. Therefore, the output terminal signal waveform of the OR gate OR _{4 which} is actually a transmission signal is the output waveform of the inverter I ₁ as shown in FIG. 8 (b) and the output of the decade counter T ₃ as shown in FIG. 8 (c). The terminal Q ₀ signal is inputted, and the same signal waveform as in FIG. 8 (d) is output.

Here, signals of terminals D ₀ and D ₁ are used as synchronization signals, and signals of terminals D ₂ , D ₃ , D ₄ , D ₅ , and D ₈ are high signals, Otherwise, a low signal will appear.

On the other hand, when there is no floor signal, a high signal is displayed on the output terminal Go of the binary decoder B as shown in FIG. 4, so that a high signal is applied to the input terminal EN of the muldy flexor M. As shown in the truth table shown in FIG. 7, the high signal is also displayed at the output terminal Zo thereof, and thus the output terminal signal of the OR gate OR ₄ is also high and no data is transmitted to the receiving unit (b). Do not.

When the transmitter transmits a transmission signal as shown in FIG. 10 (a) to the receiver (b), the waveform of the reset terminal R of the binary counter T ₄ shown in FIG. Since the inverter I ₄ is inverted, the signal waveform of FIG. 10 (b) is obtained.

As shown in FIG. 11, the binary counter T ₄ counts only while the signal is low (L) at the reset terminal R, and divides the output pulse of the pulse generator ^ㅇ '16. binary output terminal (Q ₃₎ signal and a 32-frequency divider output of the counter (T ₄₎ terminal (Q ₄₎ signal in is applied to the input aND gate (a ₈₎ output terminal of the aND gate (a ₈₎ of claim 10 (c The synchronization signal as shown in Fig. 2) is detected.

At this time, the output terminal signal of the AND gate (A ₈ ) becomes a high signal state when the clock generator turns 24 clock pulses of the pulse generator ( ^ㅇ ') from the moment when the synchronization signal is input to the input terminals (D ₀ ) and (D ₁ ). signal capacitor (C ₃₎ and a resistor binary via a (R ₁₂₎ a counter _{(T 6), (T 6} ) reset terminal (R) applied to the binary counter (T ₅₎ becomes in a, (T ₆₎ is The reset state is established.

Therefore, in the binary counter T ₅ , the count starts from the moment when the synchronization signal is detected, and the clock pulses of the pulse generator ^ㅇ 'are divided into 16 and input to the binary counter T ₆ . ₆ ) one count is counted every 16 clocks.

Therefore, each output waveform of the multiplexer LM operated as in the truth table shown in FIG. 12 is transmitted as input point in FIGS. 10 (e) to 10 (j) and is the center point of each data input. Since the high signal appears at, it is sampled sequentially.

Therefore, each data latch (DR ₁ )-(DR ₇ ) of the data latch circuit unit (K) operating as in the truth table of FIG. 13 accepts time-division data sequentially, and at this time, the signal shown in FIG. Of the waveforms, only signals (D ₂ ), (D ₃ ), (D ₄ ), (D ₅ ), and (D ₈ ) are sampled high and other signals are sampled low and data latches (DR ₁ ), ( A high signal appears at each output terminal Q of DR ₂ ), (DR ₃ ), (DR ₄ ), and (DR ₇ ).

This high signal causes the LED segments D _a (D _b ) (D _c ) (D _d ) (D _g ) to be driven through the inverter buffers I ₆ (I ₇ ) (I ₈ ) (I ₉ ). Therefore, the digital indicator (ㅁ) will display the number "∃".

The present invention operating as described above allows the elevator floor signal to be displayed on the digital indicator of the receiving station's monitoring station at a distance using one transmission line so that the elevator floor signal can be displayed without using a conventional diode matrix circuit. It is possible to transmit the signal, and to minimize the wiring signal and the number of parts, thereby simplifying the process and reducing the cost.

In particular, even when the number of floors is displayed as two digits, such as 10 or more floors, the time division transmission circuit in the transmitter and the sampling circuit in the receiver are expanded to enable signal transmission as one transmission line.

Claims (4)

A conventional segment signal input section (a), a binary signal converter section for decoding the layer signal as a binary signal, and a seven-segment signal along with the synchronization signal in accordance with the clock pulse signal of the pulse generator (O). A clock signal of the pulse generator and a sync signal detector for detecting the sync signal by receiving the transmitted signal to be divided by the transmitter. A sampling circuit section for sampling after synchronizing a synchronous signal according to the signal; a data latch circuit section for sequentially latching data according to a clock generated by the sampling circuit section; and a conventional digital LED indicator. ㅁ) The floor number display circuit for the monitoring panel of the elevator, characterized in that comprises a receiving unit (b). The elevator according to claim 1, wherein the time division transmission circuit section (a) in the transmitting section (a) and the sampling circuit section (b) in the receiving section (b) are increased in number so that the number of floors of the elevator is displayed in two digits. Floor display circuit for monitoring panel. The binary signal converting unit ( ₂ ) consisting of a binary decoder (B) and an OR gate (OR ₁ ) or (OR ₂ ) is connected to a conventional floor signal input unit (a). The multiplexer (M), binary counter (T ₁ ), (T ₂ ), decadent detector (T ₃ ), or gate through the 7-segment decoder (c) at the output of the true signal converter (ㅂ). Transmitting unit of the monitoring panel floor display circuit of an elevator, characterized in that it is configured by connecting a time division transmission circuit unit consisting of (OR ₃ ), (OR ₄ ), end gates (A ₁ -A ₇ ), and inverter (I ₁ ) end). The synchronization signal according to claim 1, wherein the output terminal of the transmitting unit (A) comprises a binary counter (T ₄ ), an end gate (A ₈ ), a resistor (R ₁₂ ), and a capacitor (C ₃ ) through an inverter (I ₄ ). A sampling circuit section consisting of a demultiplexer DM and a binary counter T ₅ -T ₆ to the sync signal detecting section (E) a data latch circuit portion (l) consisting of data latches (DR ₁ -DR ₇ ) and inverter buffers (I ₆ -I ₉ ) is connected, and the data latch circuit portion (l) is replaced with a conventional digital LED indicator ( ㅁ) receiving unit of the monitoring panel floor number display circuit of the elevator, characterized in that it is configured to be connected to (b).

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