JPS5758434A - Clock synchronizing circuit - Google Patents
Clock synchronizing circuitInfo
- Publication number
- JPS5758434A JPS5758434A JP55133562A JP13356280A JPS5758434A JP S5758434 A JPS5758434 A JP S5758434A JP 55133562 A JP55133562 A JP 55133562A JP 13356280 A JP13356280 A JP 13356280A JP S5758434 A JPS5758434 A JP S5758434A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- signal
- phase
- frequency
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To take clock synchronism simply and to use the degree of multiplexity at a maximum, by controlling the number of circulating counts of a counter counting an original clock signal. CONSTITUTION:A clock signal 31 in frequency f0 is inputted to a phase comparison circuit 32. The phase comparison circuit 32 consists of flip-flops, which compare the phase between a timing signal 33 and the clock signal 31 produced at every count from a variable period counter 37 and discriminates ''1'', ''0'' of the clock signal 31 at the rise of the timing signal 33. A control signal 34 can be obtained from the phase comparing circuit 32. A variable period counter can change the frequency dividing ratio according to ''1'' and ''0'' of the control signal 34. Thus, the synchronizing frequency with the highest efficiency can be produced.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55133562A JPS5758434A (en) | 1980-09-25 | 1980-09-25 | Clock synchronizing circuit |
DE8181107326T DE3173313D1 (en) | 1980-09-25 | 1981-09-16 | Clock synchronization signal generating circuit |
EP81107326A EP0048896B1 (en) | 1980-09-25 | 1981-09-16 | Clock synchronization signal generating circuit |
CA000386657A CA1183579A (en) | 1980-09-25 | 1981-09-25 | Clock synchronization signal generating circuit |
US06/305,712 US4475085A (en) | 1980-09-25 | 1981-09-25 | Clock synchronization signal generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55133562A JPS5758434A (en) | 1980-09-25 | 1980-09-25 | Clock synchronizing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5758434A true JPS5758434A (en) | 1982-04-08 |
JPS6144423B2 JPS6144423B2 (en) | 1986-10-02 |
Family
ID=15107698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55133562A Granted JPS5758434A (en) | 1980-09-25 | 1980-09-25 | Clock synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5758434A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60216647A (en) * | 1984-04-12 | 1985-10-30 | Toshiba Corp | Jitter elimination synchronizing equipment |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007011961A (en) * | 2005-07-04 | 2007-01-18 | Hioki Ee Corp | Clock generation device and waveform recorder |
-
1980
- 1980-09-25 JP JP55133562A patent/JPS5758434A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60216647A (en) * | 1984-04-12 | 1985-10-30 | Toshiba Corp | Jitter elimination synchronizing equipment |
Also Published As
Publication number | Publication date |
---|---|
JPS6144423B2 (en) | 1986-10-02 |
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