JP2007011961A - Clock generation device and waveform recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generation device allowing reduction of size and cost. <P>SOLUTION: This clock generation device has: a phase detection part 24 detecting phase relation of an internal clock Sc1 to an inputted external clock Sc3; and a counter 22 advancing a present count value by a prescribed number when the phase relation is a phase relation wherein the internal clock Sc1 delays to the external clock Sc3 while dividing a reference clock Sck to generate the internal clock Sc1 by executing count operation in synchronization with the reference clock Sck, and stopping count operation by a prescribed period of the reference clock Sck when the phase relation is a phase relation wherein the internal clock Sc1 advances relatively to the external clock Sc3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock generator and a waveform recorder that can synchronize an internal clock with an external clock.

As this type of clock generation device, a clock generation device (digital phase locked loop circuit) disclosed in Japanese Patent Application Laid-Open No. 11-298319 is known. This clock generator is configured by connecting a phase comparator, an up / down counter, and a variable frequency divider in a loop, and by connecting an original oscillator having a constant output frequency to the variable frequency divider. In this clock generator, the phase comparator outputs a pulse signal having a pulse width corresponding to the phase difference between the supplied input signal and the output signal of the variable frequency divider, and the up / down counter outputs the pulse signal. By outputting the count number according to the pulse width, the variable divider divides the signal output from the original oscillator using this count number as the frequency division number and feeds it back to the phase comparator The phase difference between the input signal and the output signal is gradually reduced, and both signal phases are matched after a predetermined time.
Japanese Patent Laid-Open No. 11-298319 (page 2, FIG. 3)

  By the way, in recent years, it is desired to reduce the size and the price of the clock generator. However, since the conventional clock generator described above requires two circuits, an up / down counter and a variable frequency divider, in addition to the phase comparator and the original oscillator, it is difficult to reduce the size and the cost. There is a problem of being.

  The present invention has been made to solve such a problem, and has as its main object to provide a clock generator and a waveform recorder that can be reduced in size and price.

  In order to achieve the above object, the clock generator according to claim 1 includes a phase detector for detecting a phase relationship of the internal clock with respect to the input external clock, and a reference operation by executing a counting operation in synchronization with the reference clock. And the phase relationship is a phase relationship in which the internal clock is delayed with respect to the external clock, the current count value is advanced by a predetermined number, and the phase relationship is And a counter that stops the counting operation for a predetermined period of the reference clock when the internal clock is in a phase relationship with respect to the clock.

  According to another aspect of the waveform recorder of the present invention, the input signal to be measured is converted into digital data in synchronization with the internal clock, and the internal clock is generated by dividing the reference clock. A waveform recorder comprising a clock generator for synchronizing the internal clock with the input external clock, and a controller for storing the digital data in a memory, wherein the clock generator is configured to store the internal clock with respect to the external clock. A phase detector that detects a phase relationship of the clock; and performing a count operation in synchronization with the reference clock to divide the reference clock to generate the internal clock, while the phase relationship is relative to the external clock. When the internal clock is delayed in phase relationship, the current count value is advanced by a predetermined number, and the phase relationship is Tsu when the phase relationship in which the internal clock is advanced with respect to click and a counter to stop counting a predetermined period of the reference clock.

  According to the clock generation device of the first aspect, the phase detection unit detects the phase relationship of the internal clock with respect to the input external clock, and the counter executes the count operation in synchronization with the reference clock, thereby generating the reference clock. When the detected phase relationship is a phase relationship in which the internal clock is delayed with respect to the external clock while dividing the internal clock to generate the internal clock, the current count value is advanced by a predetermined number, and the detected phase relationship is the external clock. When the internal clock is in a phase relationship where the internal clock is advanced, the count operation is stopped for a predetermined period of the reference clock, so that the internal clock is delayed or advanced when the internal clock is delayed or advanced. It is possible to correct the phase of the internal clock so as to reduce the frequency. Therefore, according to this clock generation device, unlike the configuration of a conventional clock generation device that requires four circuits, that is, an up / down counter and a variable frequency divider, together with a phase comparator and an original oscillator that generates a reference clock, 3 Since the circuit can be constituted by one circuit, that is, an original oscillator, a phase detector (phase comparator), and a counter, the number of parts can be reduced. As a result, the entire apparatus can be reduced in size and price.

  According to the waveform recorder of the second aspect, the clock generator having the same configuration as that of the clock generator is provided, so that three circuits, that is, an original oscillator, a phase detector (phase comparator), and Since it can be configured with a counter, the number of parts can be reduced. As a result, the entire apparatus can be reduced in size and price.

  The best mode of a clock generator and a waveform recorder according to the present invention will be described below with reference to the accompanying drawings.

  First, the configuration of the waveform recorder 1 will be described with reference to the drawings.

  As shown in FIG. 1, the waveform recorder 1 includes a synchronization circuit 2, an A / D conversion unit 3, a storage controller 4, a memory 5, a CPU 6, and an output unit 7, and includes waveform data D1 of the measurement target signal S1 (present invention). Digital data) can be recorded.

  The synchronization circuit 2 corresponds to a clock generation device (clock generation unit) according to the present invention, and includes an oscillation unit 21, a counter 22, a flip-flop 23, and a phase detection unit 24 as shown in FIG. It has a function of generating and synchronizing the internal clock Sc1 with the input external clock Sc2.

  The oscillating unit 21 is composed of a crystal oscillator or the like, and generates and outputs a reference clock Sck used in the waveform recorder 1. The counter 22 repeats a count operation (increment operation as an example) in synchronization with the reference clock Sck, thereby dividing the reference clock Sck (in this example, dividing by 10 as an example) to generate an internal clock with a duty of 50%. Sc1 is output. In this case, the counter 22 performs the frequency dividing operation when the control signals Ss1 and Ss2 are not input from the phase detector 24. On the other hand, when the control signal Ss1 is input, the counter 22 outputs a value obtained by adding (predetermining) a predetermined number to the current count value as the next count value in synchronization with the next reference clock Sck. Further, when the control signal Ss2 is input, the counter 22 stops the counting operation for a predetermined period (predetermined clock) of the reference clock Sck while maintaining the current count value. In this example, the predetermined number when the control signal Ss1 is input is defined as “2”, and the predetermined period when the control signal Ss2 is input is defined as “1 period”.

  The flip-flop 23 is constituted by a D-flip-flop as an example, and outputs the input external clock Sc2 as the external clock Sc3 in synchronization with the reference clock Sck. When the external clock Sc3 is input, the phase detection unit 24 is synchronized with the rising edge of the external clock Sc3 and has a pulse width corresponding to one cycle of the reference clock Sck as shown in FIGS. A signal Sc4 is generated. Further, the phase detection unit 24 is based on the pulse signal Sc4 and the internal clock Sc1, and the phase relationship between the internal clock Sc1 and the external clock Sc3 (that is, whether the internal clock Sc1 is delayed or advanced with respect to the external clock Sc3). ) Is detected, and the control signal Ss1 is output when it is delayed, and the control signal Ss2 is output when it is advanced. Specifically, as shown in FIG. 4, the phase detection unit 24 uses the period T1 of two cycles of the reference clock Sck starting from the rising edge of the internal clock Sc1, as a reference, to pulse before this period T1. When the signal Sc4 is output, the control signal Ss1 is output because the internal clock Sc1 is delayed in phase with respect to the external clock Sc3. On the other hand, as shown in FIG. 5, when the pulse signal Sc4 is output after the period T1, the phase detection unit 24 outputs the control signal because the internal clock Sc1 advances with respect to the external clock Sc3. Ss2 is output. Further, as shown in FIG. 6, when the pulse signal Sc4 is output during this period T1, the phase detector 24 controls the phase because the internal clock Sc1 is synchronized with the external clock Sc3. The signals Ss1 and Ss2 are not output. That is, this period T1 means an allowable range in which the internal clock Sc1 is considered to be synchronized with the external clock Sc2.

  The A / D converter 3 samples the input measurement target signal S1 in synchronization with the internal clock Sc1, thereby converting the measurement target signal S1 into waveform data (digital data) D1 and outputting the waveform data (digital data) D1. The storage controller 4 corresponds to the control unit in the present invention, and stores the waveform data D1 in the memory 5. Further, the storage controller 4 reads out the waveform data D1 stored in the memory 5 and outputs it to the CPU 6 in response to a request from the CPU 6. The CPU 6 reads out the waveform data D1 stored in the memory 5 via the storage controller 4 and outputs it to the output unit 7. For example, the output unit 7 includes a display device such as a printing device (printer or plotter) or a display device, and displays the input waveform data D1 in a waveform on a recording paper or a screen.

  Next, the waveform recording operation for the waveform recorder 1 will be described. As an example, an operation for recording each waveform data D1 of two types of measurement target signals S1 (S1a, S1b) while synchronizing two waveform recorders 1a, 1b as shown in FIG. 3 will be described.

  First, the respective waveform recorders 1a and 1b (hereinafter also referred to as “waveform recorder 1” unless otherwise specified) are activated, and the waveform recorder 1a starts the recording operation of the waveform data D1 for the measurement target signal S1a. Then, the waveform recorder 1b starts the recording operation of the waveform data D1 for the measurement target signal S1b. Note that the measurement target signals S1a and 1b are also referred to as “measurement target signals S1” when they are not particularly distinguished. In each waveform recorder 1, during the recording operation of the waveform data D 1, the counter 22 divides the internal clock Sc 1 to generate the internal clock Sc 1 and supplies the internal clock Sc 1 to the A / D converter 3. In synchronization with the internal clock Sc1, the measurement target signal S1 is converted into waveform data D1, and the storage controller 4 stores the waveform data D1 in the memory 5. Further, the CPU 6 reads out the waveform data D1 stored in the memory 5 through the storage controller 4 and outputs it to the output unit 7, whereby the waveform of the measurement target signal S1 is displayed on the screen or on the recording paper.

  During the recording operation of the waveform data D1, when a common external clock Sc2 is input to each waveform recorder 1, in each waveform recorder 1, the synchronization circuit 2 starts its operation and the internal clock Sc1 is synchronized with the external clock Sc2. Specifically, as shown in FIGS. 4 to 6, the flip-flop 23 synchronizes the external clock Sc2 with the reference clock Sck and outputs the external clock Sc3 to the phase detection unit 24. When the external clock Sc3 is input, the phase detector 24 generates a pulse signal Sc4 synchronized with the rising edge of the external clock Sc3 as shown in FIGS. 4 to 6, and outputs the pulse signal Sc4 for the period T1. Based on the timing, it is detected whether the internal clock Sc1 is delayed, advanced or synchronized with the external clock Sc3.

  In this case, as shown in FIG. 4, when the pulse signal Sc4 is output prior to the period T1, the phase detector 24 detects that the internal clock Sc1 has a phase relationship that is delayed with respect to the external clock Sc3. Then, the control signal Ss1 is output to the counter 22. When the control signal Ss1 is input, the counter 22 outputs a value obtained by adding a predetermined number (“2”) to the current count value as the next count value in synchronization with the next reference clock Sck. For example, when the count value when the control signal Ss1 is input is “7”, the count value “9” is output in synchronization with the next reference clock Sck. Accordingly, since the count value of the counter 22 advances by 1, the counter 22 outputs the internal clock Sc1 whose phase has been advanced by one count (one cycle of the reference clock Sck). In the figure, since the pulse signal Sc4 is output one cycle of the reference clock Sck before the period T1, the counter 22 operates as described above, so that the internal clock Sc1 is one cycle of the reference clock Sck. I'm falling early by the minute. Therefore, when the internal clock Sc1 thereafter rises, the pulse signal Sc4 is included in the period T1, and the internal clock Sc1 is synchronized with the external clock Sc3.

  On the other hand, as shown in FIG. 5, when the pulse signal Sc4 is output after the period T1, the phase detection unit 24 detects that the internal clock Sc1 has a phase relationship that advances with respect to the external clock Sc3. The control signal Ss2 is output to the counter 22. When the control signal Ss2 is input, the counter 22 stops the counting operation for one count (one cycle of the reference clock Sck) while maintaining the current count value. For example, when the count value when the control signal Ss2 is input is “7”, the count value “7” is held without being counted up even when the next reference clock Sck is input. Thus, since the count value of the counter 22 is delayed by one, the counter 22 outputs the internal clock Sc1 whose phase is delayed by one count (one cycle of the reference clock Sck). In the figure, since the pulse signal Sc4 is output after one period of the reference clock Sck from the period T1, the counter 22 operates as described above, so that the internal clock Sc1 corresponds to one period of the reference clock Sck. Just falling late. Therefore, when the internal clock Sc1 thereafter rises, the pulse signal Sc4 is included in the period T1, and the internal clock Sc1 is synchronized with the external clock Sc3.

  As shown in FIG. 6, when the pulse signal Sc4 is output during the period T1, the phase detector 24 detects that the external clock Sc3 and the internal clock Sc1 are in a synchronized phase relationship and performs control. The signals Ss1 and Ss2 are not output. Therefore, the counter 22 continues the count operation (increment operation) synchronized with the reference clock Sck without advancing or delaying the count value.

  As described above, each time the external clock Sc2 is input, when the internal clock Sc1 is delayed with respect to the external clock Sc3 (the external clock Sc2 synchronized with the reference clock Sck), the phase of the internal clock Sc1 is changed to the phase of the reference clock Sck. When the internal clock Sc1 is advanced by one period and conversely, when the internal clock Sc1 is advanced, the synchronization circuit 2 repeats the above-described operation for delaying the phase of the internal clock Sc1 by one period of the reference clock Sck. The internal clock Sc1 of the waveform recorder 1 is synchronized with the external clock Sc2, and as a result, the internal clocks Sc1 of the waveform recorders 1a and 1b are synchronized with each other. Therefore, each waveform recorder 1 records the waveform data D1 of each of the measurement target signals S1a and 1b input in synchronization with each other after a certain amount of time has elapsed from the start of recording.

  Thus, according to this synchronization circuit 2, the phase detector 24 detects the phase relationship of the internal clock Sc1 with respect to the external clock Sc3, and the counter 22 determines the detection result (detected phase relationship) of the phase detector 24. Accordingly, when the internal clock Sc1 is delayed with respect to the external clock Sc2, the current count value is advanced (specifically increased) by a predetermined number (“2”), and the internal clock Sc1 is increased with respect to the external clock Sc2. By stopping the count operation for a predetermined period (one period) of the reference clock Sck when the time is advanced, when the internal clock Sc1 is delayed or advanced with respect to the external clock Sc2, the delay or advance is caused. The phase of the internal clock Sc1 can be corrected so as to decrease. Therefore, according to this synchronization circuit 2, unlike the configuration of a conventional synchronization circuit (clock generation device) that requires two circuits of an up / down counter and a variable frequency divider together with a phase comparator and an original oscillator, Since the circuit, that is, the oscillating unit 21, the phase detecting unit 24, and the counter 22 can be configured, the number of parts can be reduced, so that the entire circuit can be reduced in size and price. The synchronization circuit 2 is configured to include the flip-flop 23 in addition to the above three circuits. However, since the synchronization circuit 2 is a very simple circuit, there is no problem in terms of space and cost.

  Further, in the waveform recorder 1 including the synchronizing circuit 2, since the synchronizing circuit 2 can be reduced in size and price, the entire apparatus can be reduced in size and the apparatus cost can be reduced accordingly. Can be realized.

  In addition, this invention is not limited to said structure. For example, the period T1 as an allowable range in which the internal clock Sc1 is considered to be synchronized with the external clock Sc2 is defined as two periods of the reference clock Sck starting from the rising edge of the internal clock Sc1. The length of the period T1 can be arbitrarily set within a range of two or more cycles of the reference clock Sck and one cycle or less of the internal clock Sc1. Further, it is possible to adopt a configuration in which the period T1 is defined starting from the falling edge of the internal clock Sc1, and the falling edge of the internal clock Sc1 is synchronized with the external clock Sc2. Further, although the counter 22 is configured to divide the reference clock Sck by performing an increment operation as an example of advancing the count value, a configuration in which the count value is advanced by performing a decrement operation may be employed. Moreover, although the example which applied the synchronous circuit 2 to the waveform recorder 1 was given and demonstrated, it can apply also to various measuring devices, such as another measuring device and a data logger.

2 is a block diagram showing a configuration of a waveform recorder 1. FIG. 2 is a block diagram showing a configuration of a synchronization circuit 2. FIG. It is a block diagram which shows the connection state at the time of synchronizing each internal clock Sc1 of the waveform recorder 1a, 1b. FIG. 10 is a timing chart for explaining the operation of the synchronization circuit 2 when synchronizing the internal clock Sc1 in a delayed state with respect to the external clock Sc2 with the external clock Sc2. FIG. 7 is a timing chart for explaining the operation of the synchronization circuit 2 when synchronizing the internal clock Sc1 in the advanced state with respect to the external clock Sc2 with the external clock Sc2. 6 is a timing chart for explaining the operation of the synchronization circuit 2 when the internal clock Sc1 is in a synchronized state with respect to the external clock Sc2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Waveform recorder 2 Synchronous circuit 3 A / D conversion part 4 Storage controller 5 Memory 21 Oscillator 22 Counter 23 Flip-flop 24 Phase detection part D1 Waveform data Sc1 Internal clock Sc2, Sc3 External clock Sck Reference clock

Claims (2)

A phase detector that detects the phase relationship of the internal clock with respect to the input external clock;
When the phase relationship is a phase relationship in which the internal clock is delayed with respect to the external clock while the internal clock is generated by dividing the reference clock by performing a count operation in synchronization with the reference clock A counter that stops the count operation for a predetermined period of the reference clock when the current count value is advanced by a predetermined number and the phase relationship is a phase relationship in which the internal clock is advanced with respect to the external clock; Clock generator. An A / D converter that converts the input signal to be measured into digital data in synchronization with the internal clock, and the internal clock is generated by dividing the reference clock, and the internal clock is synchronized with the input external clock A waveform recorder comprising a clock generator and a controller for storing the digital data in a memory,
The clock generation unit divides the reference clock to generate the internal clock by performing a count operation in synchronization with the reference clock and a phase detection unit that detects a phase relationship of the internal clock with respect to the external clock However, when the phase relationship is a phase relationship in which the internal clock is delayed with respect to the external clock, the current count value is advanced by a predetermined number, and the phase relationship is advanced by the internal clock with respect to the external clock. And a counter that stops the counting operation for a predetermined period of the reference clock when the phase relationship is in the range.

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