JPH07294616A - Method for displaying waveform for adjustment of sampling clock - Google Patents

Abstract

PURPOSE:To adjust phase of a sampling clock supplied to an A/D converter by enlarging/displaying part of triangular waves on a display screen, and making a level difference of waveforms included in the enlarged/displayed waveforms readable by eye. CONSTITUTION:In order to find phases of sampling clocks CLKI and CLK2, signals of triangular waveforms are input from an input terminal 1. The triangular waveform signals are alternately sampled at A/D converters 3a and 3b, converted into digital waveform data, and taken into a memory 6. A waveform display means 7 reads out the waveform data converted by the converters 3a and 3b from the memory 6 and displays triangular waveforms on a display screen 8. When the sampling clocks CLK1 and CLK2 are shifted 180 in phase on the enlarged waveforms, level distances (x) (=b2-a2) and (y) (=b1-a1) of the waveform data become equal to each other. A variable resistance VR of a clock-adjusting means 4 is manipulated to make the (x) and (y) equal to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display method for adjusting a sampling clock, and more specifically, in a waveform recorder having a plurality of A / D converters, each A
The present invention relates to a waveform display method used when adjusting the phase of a sampling clock supplied to a / D converter.

[0002]

2. Description of the Related Art FIG. 12 shows a conventional example of a waveform recorder having two A / D converters. According to this, the analog input signal input from the input terminal 1 is amplified by the amplifier 2 and then converted into digital waveform data by the A / D converters 3a and 3b.

In this case, the A / D converters 3a and 3b are supplied with the sampling clocks CLK1 and CLK2 whose phases are shifted from each other by 180 degrees from the clock adjusting means 4, whereby the analog input signal is converted into the two. A /
The D converters 3a and 3b are alternately sampled, and as a result, waveform data whose sampling frequency is doubled is obtained.

Sampling clocks CLK1 and CLK2
The phase of is adjusted by the variable resistor VR provided in the clock adjusting means 4.
Conventionally, check pins 5a and 5b are provided near the clock input terminals of the respective A / D converters 3a and 3b, and sampling signals obtained from the check pins 5a and 5b are observed by a time difference measuring device such as an oscilloscope and sampled. The variable resistor VR is operated so that the phases of the clocks CLK1 and CLK2 are shifted by 180 degrees.

[0005]

According to this, each A /
It is possible to adjust the phase even before adjusting the amplitude and zero position of the D converters 3a and 3b. However, if the frequency is high, the problem of time delay due to wiring occurs, so the check pin 5a and 5b are A / D converters 3a and 3
It is necessary to stand as close as possible to the clock input terminal of b.

Further, sampling clocks CLK1 and C
Even with a measuring device such as an oscilloscope that measures the phase (time difference) of LK2, there is a problem in that the higher the frequency, the more expensive the device.

The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to perform A / D conversion without setting check pins on a printed circuit board or measuring equipment such as an oscilloscope. It is an object of the present invention to provide a waveform display method for adjusting a sampling clock so that the phase of the sampling clock supplied to the instrument can be adjusted.

[0008]

In order to achieve the above object, the present invention provides a plurality of A / D converters and each of these A / D converters.
A clock adjusting means for supplying sampling clocks having different phases to the D converter, and the same analog input signal is converted into digital waveform data by the respective A / D converters and fetched in the memory. In a waveform recorder that reads the waveform data from the above and displays the input waveform on the display screen, inputs a triangular waveform as the input signal, enlarges a part of the triangular waveform on the display screen, and displays the enlarged display waveform. It is characterized in that at least either the time difference or the level difference between the respective waveform data included in (1) can be visually read.

In this case, it is preferable that each waveform data included in the enlarged display waveform is provided with a mark for identifying the A / D converter that has converted the waveform data. Further, at least a time difference or a level difference between the waveform data included in the enlarged display waveform may be directly displayed as a numerical value on a predetermined portion of the display screen.

On the other hand, as the input signal, a sine wave having a slightly different frequency with respect to the sampling clock of each A / D converter may be input. According to this, the beat waveform appearing on the output side of each A / D converter is displayed on the display screen.

In addition to the beat waveform, a reference line when the input signal is zero may be displayed. When the beat waveform is displayed on the display screen, it is preferable to change the line type for each A / D converter.

[0012]

When a triangular waveform is input, a part of it is enlarged and displayed on the display screen. When there are two A / D converters,
If the phase of the sampling clock is shifted by 180 degrees, the waveform data from each A / D converter will appear alternately at regular intervals in terms of time and level.

On the other hand, when the phase of the sampling clock is deviated from 180 degrees, the waveform data does not appear the same in terms of time and level. Therefore,
In order to adjust the phase shift to 180 degrees, for example, the variable resistance of the clock adjusting means is operated so that the waveform data by each A / D converter alternately appears at regular intervals both in terms of time and level. You can do it like this.

When a sine wave having a slightly different frequency is input to the sampling clock of each A / D converter, two beat waveforms due to each A / D converter appear on the display screen. By looking at the phases of these two beat waveforms, the phase relationship of the sampling clocks can be known. If the sampling clocks deviate from 180 degrees, the variable resistor of the clock adjusting means may be operated in the same manner as above.

[0015]

EXAMPLES Examples of the present invention will be described below. FIG. 1 shows a schematic configuration of a waveform recorder applied to the present invention. Basically, it is the same as the conventional device shown in FIG. 12 described above, but in the same figure, in addition to that, a memory 6 for storing the waveform data converted by the A / D converters 3a and 3b, The waveform display means 7 for reading the waveform data from the memory 6 and displaying it on the display screen 8 is shown.

FIG. 2 shows an example of a concrete circuit configuration of the clock adjusting means 4, and FIG. 3 shows waveform charts appearing in the respective parts of FIG. According to this, the clock adjusting means 4 includes the crystal oscillation circuit 41, and the pulse wave output from the oscillation circuit 41 rises and the fall speed is slow in the buffer circuit (or integrator) 42 shown in FIG. 2) is converted into a gentle pulse wave at both the leading edge and the trailing edge and is supplied to one input terminal of the comparator 43.

A variable resistor VR for setting a threshold voltage is connected to the other input terminal of the comparator 43, and in relation to the threshold value, the output side of the comparator 43 is as shown in FIG. 3 (b). A pulse wave appears. The same pulse wave is passed through the non-inverting buffer circuit 44 to one A / D
It is used as the sampling clock CLK1 of the converter 3a (see FIG. 3C), and is also used as the sampling clock CLK2 of the other A / D converter 3b by passing through the inverting buffer circuit 45 (FIG. 3 ( See d)).

In this embodiment, the variable resistor VR is
Is operated to vary the threshold voltage, thereby adjusting the phase between the rising edges of the sampling clocks CLK1 and CLK2.

Sampling clocks CLK1 and CLK2
In order to see the phase of, the triangular waveform signal is input from the input terminal 1 as the first embodiment. The triangular waveform signals are alternately sampled by the A / D converters 3a and 3b, converted into digital waveform data, and then stored in the memory 6. Here, for convenience of explanation, one A / D converter 3
The waveform data by a is a1, a2, a3 ... And the waveform data by the other A / D converter 3b is b1, b2, b3.
...

The waveform display means 7 reads out these waveform data from the memory 6 and displays a triangular waveform on the display screen 8 as shown in FIG. Then, according to an instruction from the operator, for example, the circled portion in FIG. 4 is enlarged and displayed.

An enlarged display example is shown in FIG.
In this case, the waveform data a by one A / D converter 3a
, 1, a2, a3 ... Are displayed in the form of square dots, whereas the waveform data b1, b by the other A / D converter 3b is displayed.
2, b3 ... Are displayed in the form of round dots so that it is possible to identify which A / D converter the waveform data is from.

In this enlarged waveform, when the phases of the sampling clocks CLK1 and CLK2 are 180 degrees out of phase, the level intervals of the respective waveform data are equal. That is, x (= b2-a2) and y (= b1-a1) in the figure
And are almost the same. On the other hand, when the phases of the sampling clocks CLK1 and CLK2 are deviated from 180 degrees, the magnitudes of x and y are different as shown in FIG.

Therefore, while looking at the enlarged display screen, the variable resistor VR of the clock adjusting means 4 may be operated so that the sizes of x and y are substantially the same. In the above embodiment, the phase shift is observed depending on the level of each waveform data, but it goes without saying that the determination may be made based on the time difference between each waveform data. The values of x and y may be directly displayed as numerical values on a predetermined portion of the display screen 8.

By the way, assuming that the resolution of the display screen 8 in the time axis direction is N, one waveform data corresponds to one unit (dot) in the time axis direction before the waveform is enlarged, and N waveform data are displayed. It On the other hand, in the case of magnifying M times, for example, one waveform data is displayed for each M dot in the time axis direction. Therefore, the display screen 8
The waveform data displayed on the whole is N / M (= integer).

The resolution in the level (vertical) direction is A /
If the resolution is equal to or higher than the resolution of the D converter, it is not necessary to expand in the level direction, but if the resolution in the level direction is less than the resolution of the A / D converter, the resolution in the level direction is set to A. It is necessary to expand the level direction so as to have the resolution of the / D converter. As the method, for example, one unit in the level direction may be assigned to the minimum unit (1 LSB) of the waveform data.

Further, when the phase adjustment rate is within ± L%, the change amount between sampling data is 100 / L.
The triangular waveform may be input to the input terminal 1 so that (LSB) or more.

Next, a second embodiment of the waveform display using the beat waveform will be described. Generally, in an A / D converter, for example, when a sampling clock is set to 100 MHz and a 99 MHz sine wave is input to its analog input terminal, equivalent sampling causes a difference of 1 MHz on the output side of the A / D converter. A sine wave appears. This sine wave is called a beat waveform.

In adjusting the phase, a sine wave having a frequency slightly lower (or higher) than the frequencies of the sampling clocks CLK1 and CLK2 is input to the analog input terminal 1. As a result, the beat waveforms BW1 and BW2 by the A / D converters 3a and 3b are displayed on the display screen 8 as shown in FIG. In the case of the figure, since the beat waveforms BW1 and BW2 are shifted by a half cycle, the phases of the sampling clocks CLK1 and CLK2 are 180.
It is judged that they are out of alignment.

On the other hand, as shown in FIG. 8, when the beat waveforms BW1 and BW2 are deviated,
Focusing on the intersections A and B, the variable resistor VR of the clock adjusting means 4 may be operated so that the intersections A and B have the same height (level). In this connection, FIG. 9 exemplifies a case where the amplitudes of the beat waveforms BW1 and BW2 and the zero position are different in relation to this, but in such a case, the intersection points A and B of both waveforms have the same height. Sampling clocks CLK1 and CL
The phase of K2 can be accurately shifted by 180 degrees.

10 and 11 show display screens of the third embodiment corresponding to the other embodiments of the second embodiment. That is, in the embodiment, two A /
In addition to the beat waveforms BW1 and BW2 by the D converters 3a and 3b, the reference line BL when the analog input is zero is used.

In this case, attention is paid to the reference line BL and the falling intersections A and C of one beat waveform BW1 and the rising intersection B of the reference line BL and the other beat waveform BW2. According to this, the sampling clock CLK1, from the time Q between the intersections A and C and the time P between the intersections A and B
The phase of CLK2 is known.

That is, if P = Q / 2 as shown in FIG. 10, the phases of the sampling clocks CLK1 and CLK2 are 180 degrees out of phase, and if P ≠ Q / 2 as shown in FIG. 11, the sampling clock CLK1. , CLK2 are out of phase with each other by 180 degrees. In such a case, the variable resistor VR of the clock adjusting means 4 is operated to set P = Q / 2.
It should be adjusted so that

In each of the above embodiments, two A / D converters are used, but two or more A / D converters having the same analog input are used.
The present invention can be applied even when the phases of the respective sampling clocks are distributed to the A / D converters and divided by the number of the A / D converters. Further, although the phase adjustment of the sampling clock is performed by the variable resistor VR of the clock adjusting means 4, the present invention is not limited to this, and a time adjusting means such as a delay line may also be used. it can.

[0034]

As described above, according to the present invention,
The following effects are achieved. That is, a triangular waveform is input as an input signal, a part of the triangular waveform is enlarged and displayed on the display screen, and at least either the time difference or the level difference between the waveform data included in the enlarged display waveform is visually read. According to the first aspect of the invention, it is only necessary to prepare a triangular wave oscillator, and it is not necessary to set check pins on an expensive oscilloscope or a printed circuit board.

For each waveform data included in the enlarged display waveform,
According to the invention of claim 2, wherein a mark for identifying the converted A / D converter is added, it becomes easier to read the time difference and the level difference between the waveform data.

The invention according to claim 3, wherein at least a time difference or a level difference between the waveform data included in the enlarged display waveform is directly displayed as a numerical value on a predetermined portion of the display screen. According to this, the phase adjustment operation can be performed more accurately.

A sine wave having a slightly different frequency from the sampling clock of each A / D converter is input as an input signal, and a beat waveform appearing on the output side of each A / D converter is displayed on the display screen. According to the invention described in claim 4 in which the display is performed and the reference line when the analog input is set to zero, the amplitude of each A / D converter and Even if the zero position is not adjusted accurately, the phase of each sampling clock can be adjusted. Further, since the frequency of the beat waveform can be freely selected, extending the period thereof enables more accurate phase adjustment. Furthermore, even if the clock frequency becomes high, an expensive measuring instrument is not required.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing the configuration of a waveform recorder applied to the present invention.

FIG. 2 is a specific circuit diagram of clock adjusting means incorporated in the waveform recorder.

FIG. 3 is a waveform diagram showing signal waveforms at various parts of the clock adjusting means.

FIG. 4 is an explanatory diagram for explaining the first embodiment.

FIG. 5 is an explanatory diagram for explaining the first embodiment.

FIG. 6 is an explanatory diagram for explaining the first embodiment.

FIG. 7 is an explanatory diagram for explaining a second embodiment.

FIG. 8 is an explanatory diagram for explaining a second embodiment.

FIG. 9 is an explanatory diagram for explaining a second embodiment.

FIG. 10 is an explanatory diagram for explaining a third embodiment.

FIG. 11 is an explanatory diagram for explaining a third embodiment.

FIG. 12 is a block diagram showing a conventional waveform recorder.

[Explanation of symbols]

 1 analog input terminal 2 amplifier 3a, 3b A / D converter 4 clock adjusting means 6 memory 7 waveform display means 8 display screen

Claims (6)

[Claims] 1. A plurality of A / D converters and respective A / D converters
A clock adjusting means for supplying sampling clocks having different phases to the D converter, and the same analog input signal is converted into digital waveform data by the respective A / D converters and fetched in the memory. In a waveform recorder that reads the waveform data from the above and displays the input waveform on the display screen, inputs a triangular waveform as the input signal, enlarges a part of the triangular waveform on the display screen, and displays the enlarged display waveform. A method for displaying a waveform for adjusting a sampling clock, wherein at least either a time difference or a level difference between the waveform data included in the above can be read visually. 2. The waveform data included in the enlarged display waveform is provided with a mark for identifying the A / D converter converted from the waveform data. Waveform display method for sampling clock adjustment. 3. The display device is characterized in that at least a time difference or a level difference between waveform data included in the enlarged display waveform is directly displayed as a numerical value on a predetermined portion of the display screen. The waveform display method for adjusting a sampling clock according to claim 1. 4. A plurality of A / D converters and respective A / D converters
A clock adjusting means for supplying sampling clocks having different phases to the D converter, and the same analog input signal is converted into digital waveform data by the respective A / D converters and fetched in the memory. In the waveform recorder that reads the waveform data from the above and displays the input waveform on the display screen, input a sine wave having a slightly different frequency with respect to the sampling clock of each A / D converter as the input signal, A waveform display method for adjusting a sampling clock, wherein a beat waveform appearing on the output side of each A / D converter is displayed on the display screen. 5. A waveform for adjusting a sampling clock according to claim 4, wherein a reference line when the input signal is set to zero is displayed on the display screen in addition to the beat waveform. Display method. 6. The sampling clock adjusting device according to claim 4, wherein the line type is changed for each A / D converter when the beat waveform is displayed on the display screen. Waveform display method.