JPS5750474A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5750474A JPS5750474A JP12578180A JP12578180A JPS5750474A JP S5750474 A JPS5750474 A JP S5750474A JP 12578180 A JP12578180 A JP 12578180A JP 12578180 A JP12578180 A JP 12578180A JP S5750474 A JPS5750474 A JP S5750474A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- integration
- mask
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 230000010354 integration Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To increase the integration of a semiconductor device, by a method wherein, after a layer used for a gate electrode as its material has been selectively oxidized, the gate is formed by removing the layer except its peripheral part in the form of a triangle cross-section. CONSTITUTION:A p type Si substrate 1 is provided with, via a oxidized film 23, a poly Si layer 6, which is selectively oxidized with Si3N4, etc. as a mask to form SiO2 layers 14, 15. After a photoresist layer 4 with a specified pattern has been formed, the poly Si layer exposed through the RIE method is vertically etched to form a gate electrode 7 with a triangular cross section. Then the SiO2 layer exposed with the photoresist 4 as a mask is etched to form an E/D type inverter by means of diffusion, electrode evaporation, etc. By so doing, it is possible to readily form a minute pattern less than 1mum thick and consequently increase to a large extent the integration of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12578180A JPS5750474A (en) | 1980-09-10 | 1980-09-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12578180A JPS5750474A (en) | 1980-09-10 | 1980-09-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5750474A true JPS5750474A (en) | 1982-03-24 |
Family
ID=14918682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12578180A Pending JPS5750474A (en) | 1980-09-10 | 1980-09-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5750474A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0828291A2 (en) * | 1996-09-09 | 1998-03-11 | Delco Electronics Corporation | Fine pitch via formation using diffusion patterning techniques |
-
1980
- 1980-09-10 JP JP12578180A patent/JPS5750474A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0828291A2 (en) * | 1996-09-09 | 1998-03-11 | Delco Electronics Corporation | Fine pitch via formation using diffusion patterning techniques |
| EP0828291A3 (en) * | 1996-09-09 | 1999-11-17 | Delco Electronics Corporation | Fine pitch via formation using diffusion patterning techniques |
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