JPS5749270A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5749270A
JPS5749270A JP12485180A JP12485180A JPS5749270A JP S5749270 A JPS5749270 A JP S5749270A JP 12485180 A JP12485180 A JP 12485180A JP 12485180 A JP12485180 A JP 12485180A JP S5749270 A JPS5749270 A JP S5749270A
Authority
JP
Japan
Prior art keywords
polycrystalline
substrate
gate electrode
sio2
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12485180A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12485180A priority Critical patent/JPS5749270A/en
Publication of JPS5749270A publication Critical patent/JPS5749270A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823406—Combination of charge coupled devices, i.e. CCD, or BBD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To contrive improvement in characteristics, by a method wherein SiO2 and polycrystalline Si are piled up on an Si substrate to form a given pattern, which is coated with polycrystalline Si and oxidized, as well as the substrate surface is oxidized to form SiO2, and the second gate electrode is selectively provided. CONSTITUTION:On an Si substrate 11, a gate oxide film 12, a first gate electrode layer 13 of polycrystalline Si and Si3N4 14 are piled up, and a given pattern is formed. Impurity ions with the same conductivity type as the substrate are injected 15 into the exposed Si substrate 11, and the whole surface is coated with polycrystalline Si 16, the thickness thereof being less than 1/2 of the second gate oxide film. This is treated in a high-temperature O2 to from SiO2 17 at the whole of the layer 16 and the surface of the layer 15 and the ends of the first gate electrode layer 13. As a result, the contact between the film 17 and the substrate 11 is made excellent, so that a gate electrode of good quality can be obtained. Then, polycrystalline Si 18 for the second gate electrode is applied. Owing to the presence of the Si3N4 14, the polycrystalline Si 13 is unchanged in film thickness,so that there is no change in the stepped shape of the surface, and the SiO2 is formed thick only on the side surfaces. Accordingly, it is possible to prevent a short circuit between the electrodes 13 and 18.
JP12485180A 1980-09-09 1980-09-09 Manufacture of semiconductor device Pending JPS5749270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12485180A JPS5749270A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12485180A JPS5749270A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5749270A true JPS5749270A (en) 1982-03-23

Family

ID=14895657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12485180A Pending JPS5749270A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5749270A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120276A (en) * 1974-03-05 1975-09-20
JPS51142278A (en) * 1975-06-02 1976-12-07 Nec Corp Insulated-gate type fet
JPS52144288A (en) * 1976-05-26 1977-12-01 Fujitsu Ltd Preparation of electrode in semiconductor device
JPS54151374A (en) * 1978-04-14 1979-11-28 Toshiba Corp Manufacture for semiconductor device
JPS558008A (en) * 1978-06-30 1980-01-21 Toshiba Corp Semi-conductor device manufacturing method
JPS5536976A (en) * 1978-09-05 1980-03-14 Sanyo Electric Co Ltd Production of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120276A (en) * 1974-03-05 1975-09-20
JPS51142278A (en) * 1975-06-02 1976-12-07 Nec Corp Insulated-gate type fet
JPS52144288A (en) * 1976-05-26 1977-12-01 Fujitsu Ltd Preparation of electrode in semiconductor device
JPS54151374A (en) * 1978-04-14 1979-11-28 Toshiba Corp Manufacture for semiconductor device
JPS558008A (en) * 1978-06-30 1980-01-21 Toshiba Corp Semi-conductor device manufacturing method
JPS5536976A (en) * 1978-09-05 1980-03-14 Sanyo Electric Co Ltd Production of semiconductor device

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