JPS5743410A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5743410A
JPS5743410A JP55119330A JP11933080A JPS5743410A JP S5743410 A JPS5743410 A JP S5743410A JP 55119330 A JP55119330 A JP 55119330A JP 11933080 A JP11933080 A JP 11933080A JP S5743410 A JPS5743410 A JP S5743410A
Authority
JP
Japan
Prior art keywords
wafer
face
ingot
cut
notch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55119330A
Other languages
Japanese (ja)
Inventor
Masamichi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55119330A priority Critical patent/JPS5743410A/en
Publication of JPS5743410A publication Critical patent/JPS5743410A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To faicilitate the identification of the cutting position of and the front and the back of a wafer by forming an oblique notch on the orientation flat of a crystalline ingot. CONSTITUTION:The ton end face 4 of an Si single crystalline ingot 1 is an upper end and the tail end face 5 is a lower end at the time of pulling up the Si single crystal. The rectangular surface of the orientation flat 1 of the ingot 1 is divided equally in parallel at the side, an oblique notch 3 is formed at one region, and then the end face of the ingot 1 is cut in parallel, thereby forming a wafer. Thus, it is understood from the drawing that the wafer 6 is cut in the vicinity of the top end face 4, and the wafer 7 is cut in the vicinity of the tail end face 5. Since the cutting position of and the front and the back of the wafer can be identified according to the position of the notch in this manner, the magnitude of the densities of the oxygen and carbon in the wafers 6, 7 can be obtained.
JP55119330A 1980-08-29 1980-08-29 Manufacture of semiconductor device Pending JPS5743410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55119330A JPS5743410A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55119330A JPS5743410A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5743410A true JPS5743410A (en) 1982-03-11

Family

ID=14758799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55119330A Pending JPS5743410A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5743410A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783225A (en) * 1982-07-30 1988-11-08 Hitachi, Ltd. Wafer and method of working the same
JPH01113812U (en) * 1988-01-22 1989-07-31
US5230747A (en) * 1982-07-30 1993-07-27 Hitachi, Ltd. Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer
US5279992A (en) * 1982-07-30 1994-01-18 Hitachi, Ltd. Method of producing a wafer having a curved notch
WO2008151649A1 (en) 2007-06-13 2008-12-18 Conergy Ag Method for marking wafers
CN102364699A (en) * 2011-06-30 2012-02-29 常州天合光能有限公司 Marking method for ingot casting polycrystalline silicon slice head and tail sequencing
DE102010060908A1 (en) 2010-11-30 2012-05-31 Q-Cells Se Method for marking semiconductor wafer used in manufacturing process of solar cell, involves printing information including process parameters in edge of wafer
US11854995B2 (en) * 2020-04-29 2023-12-26 Semiconductor Components Industries, Llc Supports for thinned semiconductor substrates and related methods

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783225A (en) * 1982-07-30 1988-11-08 Hitachi, Ltd. Wafer and method of working the same
US5230747A (en) * 1982-07-30 1993-07-27 Hitachi, Ltd. Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer
US5279992A (en) * 1982-07-30 1994-01-18 Hitachi, Ltd. Method of producing a wafer having a curved notch
USRE40139E1 (en) * 1982-07-30 2008-03-04 Renesas Technology Corp. Wafer having chamfered bend portions in the joint regions between the contour of the cut-away portion of the wafer
JPH01113812U (en) * 1988-01-22 1989-07-31
WO2008151649A1 (en) 2007-06-13 2008-12-18 Conergy Ag Method for marking wafers
DE102010060908A1 (en) 2010-11-30 2012-05-31 Q-Cells Se Method for marking semiconductor wafer used in manufacturing process of solar cell, involves printing information including process parameters in edge of wafer
CN102364699A (en) * 2011-06-30 2012-02-29 常州天合光能有限公司 Marking method for ingot casting polycrystalline silicon slice head and tail sequencing
US11854995B2 (en) * 2020-04-29 2023-12-26 Semiconductor Components Industries, Llc Supports for thinned semiconductor substrates and related methods

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