JPS574119A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS574119A
JPS574119A JP7739180A JP7739180A JPS574119A JP S574119 A JPS574119 A JP S574119A JP 7739180 A JP7739180 A JP 7739180A JP 7739180 A JP7739180 A JP 7739180A JP S574119 A JPS574119 A JP S574119A
Authority
JP
Japan
Prior art keywords
groove
gaas
active layer
sapphire
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7739180A
Other languages
Japanese (ja)
Inventor
Kenya Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7739180A priority Critical patent/JPS574119A/en
Publication of JPS574119A publication Critical patent/JPS574119A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To facilitate formation of winding and to perform perfectly isolation between element when an active layer consisted of an islant-type compound semiconductor of GaAs, etc., is to be provided on an insulating monocrystalline substrate of sapphire, etc., by a method wherein at least one side thereof is made to be formed in parallel with the [110] direction of the crystal of the active layer. CONSTITUTION:On the insulating monocrystalline substrate 1 of sapphire, beryllia, spinel, etc., a groove 2 is formed as to make the major axial direction thereof to come in parallel with the [110] direction of the GaAs layer made to grow epitaxially on the substrate 1. Then a gate 3 at the center part of the groove 2, and a drain 5 and a source 4 positioned at both the sides thereof are formed, and are made as a GaAs FET element 6 having the active region in the groove 2. Accordingly because the semiconductor element is provided in the groove 2, no disconnection is generated when wiring is to be performed, and because the epitaxial layer of the active layer can be formed thickly, characteristic of the element becomes favorable, and also the surface thereof becomes as flat to facilitate formation of the element.
JP7739180A 1980-06-09 1980-06-09 Semiconductor device and its manufacture Pending JPS574119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7739180A JPS574119A (en) 1980-06-09 1980-06-09 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7739180A JPS574119A (en) 1980-06-09 1980-06-09 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS574119A true JPS574119A (en) 1982-01-09

Family

ID=13632587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7739180A Pending JPS574119A (en) 1980-06-09 1980-06-09 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS574119A (en)

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