JPS5738029A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5738029A
JPS5738029A JP11314080A JP11314080A JPS5738029A JP S5738029 A JPS5738029 A JP S5738029A JP 11314080 A JP11314080 A JP 11314080A JP 11314080 A JP11314080 A JP 11314080A JP S5738029 A JPS5738029 A JP S5738029A
Authority
JP
Japan
Prior art keywords
data
signal
circuit
input pulse
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11314080A
Other languages
Japanese (ja)
Inventor
Munehiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11314080A priority Critical patent/JPS5738029A/en
Publication of JPS5738029A publication Critical patent/JPS5738029A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Landscapes

  • Microcomputers (AREA)

Abstract

PURPOSE:To give a count function, by using a part of area of data memory in one- chip microcomputer for the count of input pulse and adding 1 to this memory area when an input pulse is present. CONSTITUTION:When an input pulse PIN is detected at a count controlling circuit 23, the circuit 23 outputs control signal TC1 and TC code during the next cycle after the end of instruction. The TC code is decoded at an instruction decoder ID9, the output operation of the signal II is stopped, and the output of an incrementor INC11 is applied to a program counter input register PCI13. A data designated at an address selection circuit 20 is read out from a data memory 14 with the stop release of the signal II, it is applied to a program counter PC3 and added at the INC11. The data added at the readout position of the data memory 14 is written in with the data write-in signal of the circuit 23 and counted.
JP11314080A 1980-08-18 1980-08-18 Counter circuit Pending JPS5738029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11314080A JPS5738029A (en) 1980-08-18 1980-08-18 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11314080A JPS5738029A (en) 1980-08-18 1980-08-18 Counter circuit

Publications (1)

Publication Number Publication Date
JPS5738029A true JPS5738029A (en) 1982-03-02

Family

ID=14604571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11314080A Pending JPS5738029A (en) 1980-08-18 1980-08-18 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5738029A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598434A (en) * 1982-07-06 1984-01-17 Meidensha Electric Mfg Co Ltd Time division integrated counter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598434A (en) * 1982-07-06 1984-01-17 Meidensha Electric Mfg Co Ltd Time division integrated counter

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