JPS598434A - Time division integrated counter - Google Patents

Abstract

PURPOSE:To reduce the mounting space and to simplify the hardware, by obtaining a counter output subjected to time division at each channel with an output latching a counter output stored temorarily in an RAM. CONSTITUTION:A channel designation signal fd is sent to a scanner 16 and an RAN 12 from a channel forming counter 20 with a timing signal TM1 issued from a timing circuit 18, and a scanner 16 outputs ''0'' or ''1'' to an ROM 10 by the presence of the counter input. Further, the ROM 10 produces a counter output as the firmware based on this signal and a feedback signal Inf. Then, the outpt of the ROM 10 is written in the RAM 12 with a timing signal TM3 and read out and then sent to a latch circuit 14. Then, the latch output of a circuit 14 outputs a counter signal P subjected to time division at each new channel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division set counter, and more particularly to a time division set counter in which counter output is generated as a firmware. .

When a multi-channel counter is constructed using a conventional hard logic circuit, as shown in Fig. 1, a large number of counter inputs 1 to 5 are input, and the counter elements are set corresponding to the input channels. C1 to Cn were provided, and a circuit had to be constructed for each channel. For this reason, an extremely large amount of mounting space was required, and a lot of time was required for verification.

The present invention has been made in consideration of the above points, and is a time-division aggregation type counter that enables time-division processing of multi-channel counter operations, reduces mounting space, simplifies hardware, and reduces the time required for verification. The aim is to provide the following. In order to achieve this object, the present invention includes a ROM that generates the counter output as 7 armware, and a ROM that generates the counter output as 7 armware.
A RAM that temporarily stores the readout output for each channel from the OM and a latch circuit that latches the output of the RAM are connected in series, and the output of the latch circuit is connected to the R
OM K Feed back and configure the counting processing section.

Based on the counter input input to the counting processing section and the feedback data, a counter output corresponding to each channel is generated in the ROM, and the value temporarily stored in the RAM K is latched from this counter output. The feature is that a time-divided counter output is obtained for each channel based on the output.

Hereinafter, one embodiment of the present invention will be described with reference to the attached drawings. FIG. 2 is a block diagram showing an embodiment of the time division set counter according to the present invention.

10 is R generated as counter output firmware
ot! , 12 is an R/LM that temporarily stores the readout output for each channel from this ROM 10, and 14 is a latch circuit that latches the output of the RAM 12.
4'i is connected in series and the output Y of the latch circuit 14
ROM 10 [constitutes a counting processing section CP by providing feedback. , and 16 is a selection input section composed of, for example, a scanner, from which a counter input corresponding to the collar number channel can be selected. 18 is a timing signal TM1 to the channel creation counter described later #latch circuit 1
This timing circuit generates the output timing signal TM2° of the RAM 12 and the read/write signal TM of the RAM 12. 2o is a channel generation counter that performs a counting operation in response to the timing signal TM+ from the timing circuit 18 and generates a channel designation output.

One embodiment of the present invention is configured as described above, and its operation will be explained next. 3rd solid) to (D) are operation timing charts of each part in Figure 2, C is E (the latest data of OM, P is the stored content, N is the program output of ROM, n*n+1. is the channel number It is.

□ Timing signal TMI K from timing circuit 18 as shown in Figure 3) Channel creation counter 20
The channel specified output fd from the scanner 16 and RAM
12K supplied. As a result, the scanner 16 outputs l □ l or 11' and inputs it into the ROM 10 depending on whether there is a counter input in the designated channel. At this time, the RAM 12 is in an addressing state as shown in FIG. 3 (tD) according to the designated channel. The ROM 10 executes the so-called firmware by executing the stored microprogram based on the input from the scanner 16 described above and the feedback input Inf shown in FIG. The counter output is generated as the latest data in the ROM 10 shown in the IC (FIG. 3(1m)). The third one that occurs next
RO from timing signal TM3 K shown in Figure (C1)
The output of M10 is written as 1 into the RAM 12, read out, and updated to new data as shown in Figure M3 (G). Furthermore, the third
1 old) is the output of RAM 12, PO is RAM until the previous time
The data stored in 12 is shown. This RAM 12
The output that has been updated to 0 is latched by a latch circuit 14, and the latch output from this latch circuit 14 becomes a counter output P that is time-divided for each new channel. Figure 3 (I
) indicates the previous output P.

In the above embodiment, the case where it is configured as an integration counter has been explained, but by selecting the firmware of ROM'IO, it is also possible to configure it as a timer counter or an up/down counter, for example. . ROM for timer/counter
10 [A set/reset control terminal is added, and in the case of an up/down counter, a ROM 10 K is added.
It is sufficient to add up/down control terminals.

Since the time-sharing set counter according to the present invention is as described above, it is possible to perform time-sharing processing of multi-channel counter operations, reducing the mounting space, simplifying the hardware by sharing all channels of ROM, and reducing the time required for verification. At the same time, it is possible to reduce

It is extremely easy to change and expand the counter function by selecting the firmware that generates the counter output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a conventional multi-channel counter, FIG. 2 is a block diagram of an embodiment of a time division set counter according to the present invention, and FIGS.
) shows the operation timing chart of each part of the time-division aggregation type counter of FIG. CP...Counting processing unit, 10...ROM, 12...
RAM. 14...Latch circuit, 16...Scanner, 1B.
...Timing circuit, 20...Channel creation counter.

Claims (1)

[Claims] (11 R generating counter output as firmware)
An OM, an Oboro that temporarily stores the readout output for each channel from the ROM, and a latch circuit that latches the output of the RAM are connected in series, and the output of the latch circuit is fed back to the ROM for counting processing. A selection unit that selects counter inputs corresponding to a plurality of channels for the counting processing unit, and a channel generation counter that performs a counting operation in accordance with a predetermined timing signal and generates a channel designated output. , in the selection input section, the counter input selected according to the channel designation output from the channel generation counter L6 and the R
A counter output corresponding to each channel is generated in the ROM based on the feedback input to the OM, and this counter output is sent to a predetermined address in the RAM specified by the channel designation output from the channel generation counter at a predetermined timing. A time-division aggregation type counter, characterized in that a time-division counter output is obtained for each channel by a latch output that is written to the latch circuit and read out to the latch circuit, and is output from the latch circuit at a predetermined timing. 1. (2) A self-destructing time-division aggregation counter as claimed in claim 1, wherein the selection input section is a scanner. [31] The time according to claim 1 or 2, wherein the counting processing section is made to function as an up/down counter or a timer counter by selecting the firmware stored in the ROM. Divided set counter