JP2694821B2 - Interrupt processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an interrupt processing system,
In particular, the present invention relates to an interrupt processing method used when requesting interrupt processing to an operating CPU in response to an emergency processing request.

[0002]

2. Description of the Related Art FIG. 4 shows a block diagram of an example of a conventional interrupt processing system. This conventional example is disclosed in JP-A-1-184546.
FIG. 3 is a block diagram showing an interrupt control means in a microcomputer disclosed in Japanese Patent Publication No. JP-A-2003-242, in which the interrupt control means is a CPU 4 which is a target of an interrupt processing request.
Corresponding to 4, 2-bit interrupt request counters 21 to 2
Interrupt request flag 20 including 3 and latches 28 to 30,
OR circuits 25 to 27 and 36 to 40, AND circuit 31
~ 35 and the AND circuit 41 ~.
And 43.

In the interrupt request flag 20 of FIG. 4,
Corresponding to the input of the processing request signals 125, 126 and 127, the corresponding interrupt request counters 21, 22 respectively.
And 23, the count-up is performed each time each of these processing request signals becomes active.
The counter decrement signals 139, 140 and 141 output from the D circuits 41, 42 and 43 are input to be decremented. From each of these interrupt request counters, when the processing request signal is generated once, the lower level request signals 131, 132 and 133 are output at the active level respectively, and when the processing request signal is generated twice or more. The high-level request signals 128, 129, and 130 are output at the active level, and are input to the priority control unit 24. In the priority processing of the priority control unit 24, the priority order of these request signals is as follows: upper level request signal 128> upper level request signal 129> upper level request signal 130> lower level request signal 131> lower level The request signal 132> lower level request signal 133 is determined. The contents of the interrupt request flag 20 are read by the CPU 44 via the bus 142.

The priority control section 24 receives the high level request signals 128, 129 and 130 and the low level request signals 131, 132 and 133 output from the respective request counters of the interrupt request flag 20, and
The selection signals 136, 137 and 13 are selected from the request content.
8 is output, the priority of each request signal is appropriately changed, the interrupt request signal 134 becomes active and is input to the CPU 44, and in response to this, the CPU 44
, The program process being executed is interrupted, the acknowledge signal 135 is output, and the AND circuits 41 and 42 are output.
And 43. These AND circuits 41, 4
For 2 and 43, the selection signals 136, 137
And 138 are also input, and the counter decrement signals 139, 140 and 141 are output and input to the corresponding request counters 21, 22 and 23, respectively, as described above.

Next, as an operation example, a processing request signal 125
When the interrupt processing content of the request counter 22 is already input and held in the request counter 22, that is, the value in the request counter 22 is “1” in response to the input of the processing request signal 125.
Now, the operation when a plurality of processing request signals 124 and 125 are input again in a state in which the lower level request signal 132 output from the request counter 22 is already at the active level will be described. In this case, receiving the processing request signals 124 and 125,
The interrupt request counters 21 and 22 are incremented by 1, respectively, and the lower level request signal 131 and the upper level request signal 129 are activated and input to the priority control section 24. As described above, the priority of the processing request is the higher level request signal 129> the lower level request signal 131, whereby the priority control unit 24 selects the upper level processing request 129 and makes a corresponding selection. The signal 137 becomes active and is output.

Subsequently, the interrupt request signal 134 is activated and input to the CPU 44, the program processing being executed in the CPU 44 is interrupted, and the interrupt acknowledge signal 135 is output and input to the AND circuits 41, 42 and 43. It The AND circuit 42 receives the active selection signal 137 and the interrupt acknowledge signal 135, outputs the counter decrement signal 140, and inputs it to the interrupt request counter 22. As a result, the interrupt request counter 22 is decremented by 1.
Of course, in this case, the counter decrement signal to the interrupt request counter 21 is low level,
The held value is held as "1" without change. Further, in this case, since the CPU 44 confirms that the value held in the interrupt request counter 22 is not “0” when reading the contents of the interrupt request counter 22, the interrupt request counter 22 It is possible to detect the situation where the processing request 126 is generated again while the processing request 126 is held in 22.

[0007]

In the above-mentioned conventional interrupt processing method, as means for confirming the occurrence of a plurality of processing requests in the interrupt request flag in response to the case where the processing requests occur a plurality of times. Since a plurality of request counters are built in, there is a drawback that the circuit scale becomes large.

[0008]

According to an interrupt processing method of the present invention, an interrupt processing for receiving an interrupt request signal for an information processing device executing a program processing and executing the interrupt processing during a predetermined interrupt processing acceptance period. In the method, outside the acceptance period of the interrupt processing, a predetermined level value for determining the occurrence of the first interrupt request signal is stored in response to the input of the first interrupt request signal, and the predetermined level value is stored in the predetermined level value. While outputting the corresponding first signal, the predetermined level value is inverted by the interrupt reception signal of a predetermined level in response to the input of the first interrupt request signal during the reception period of the interrupt processing. Interrupt request signal
Is stored, and a first interrupt occurrence count storage means for outputting a first signal corresponding to the inversion level value, and the i-th (i = 1, 2, 3, ..., N). -1) is connected in series to the interrupt occurrence number storage means in series,
Outside the acceptance period of the interrupt processing, the i-th interrupt
The interrupt request signal has already been generated i times in the occurrence count storage means.
Is stored, a predetermined level value for determining the generation of the [i + 1] th interrupt request signal is stored in response to the input of the [i + 1] th interrupt request signal, and the predetermined level value is stored. The output of the [i + 1] th signal is performed, and during the interrupt processing acceptance period, in response to the input of the [i + 1] th interrupt request signal, the predetermined level is transmitted via the interrupt acceptance signal of a predetermined level. The value is inverted and stored, and the [i + 1] th corresponding to the inversion level value is stored.
And an [i + 1] th interrupt occurrence count storage means for outputting a signal of (1). By referring to the storage level value in the i-th interrupt occurrence count storage means, it is possible to request / accept an interrupt process. The feature is to confirm the background.

It should be noted that the first interrupt occurrence count storage means includes a logical sum circuit for receiving the interrupt request signal and a predetermined first feedback signal, performing a logical sum operation on the logical sum, and outputting the logical sum circuit. The output signal and the system clock are input, the first signal is output in synchronization with the system clock, and output by the interrupt acceptance signal or reset signal.
Force can be reset, it is constituted by a flip-flop circuit further inputs the first signal to the OR circuit as the first feedback signal, wherein the [i +
1] the interrupt generation frequency storage means outputs the interrupt request signal and the i-th interrupt generation frequency storage means.
A logical product circuit for inputting and performing a logical product operation and outputting the logical product, and an logical sum circuit for inputting an logical output of the output signal of the logical product circuit and a predetermined i-th feedback signal and outputting the logical product. , An output signal of the OR circuit and a system clock are input, an i-th signal is output in synchronization with the system clock, and an interrupt acceptance signal or a reset signal is output.
Can be reset more output, may be constituted by a flip-flop circuit further receives a signal of the i-th to the OR circuit as a feedback signal of the i-th.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the OR circuit 1 and the D flip-flop 3 which function as a first interrupt request number storage means, and the second CPU corresponding to the CPU 8 which is the target of the interrupt processing request. An AND circuit 2, an OR circuit 5 and a D flip-flop 7 functioning as an interrupt request count storage means, and AND circuits 2 and 6 related to the reset function are provided. FIG.
(A), (b), (c), (d), (e), (f),
(G), (h) and (i) are operation timing charts of signals of respective parts in this embodiment, and the AND circuit 2 respectively.
And 6, a reset signal 104 input to the AND circuit 2, an interrupt acceptance signal 105 input to the AND circuit 2, a reset signal 106 for the D flip-flop 3, and a system clock 102 input to the D flip-flops 3 and 7.
An interrupt request signal 101 input to the R circuit 1, a signal 103 output from the OR circuit 1 and input to the D flip-flop 3, and an AND output from the D flip-flop 3
A signal 107 input to the circuit 4, a signal 108 output from the OR circuit 5 and input to the D flip-flop 7, and a signal 110 output from the D flip-flop 7 are shown.

In FIG. 1, the reset signal 104 (see FIG. 2A) input to the AND circuit 2 is at a high level while the CPU 8 is executing a predetermined program process, and the interrupt acceptance signal is received. 105 (see FIG. 2B) is also at a high level , and the software
The reset signal 109 is also held at the high level . In this state, the AND circuit 2
The reset signal 106 (see FIG. 2A) that is output from the AND circuit 6 is output from the AND circuit 6 in response to the input of the reset signal 104 and the reset signal 109. The reset signal is also input to the D flip-flop 7 in the high level state. In this case, signals 107 and 110 output from D flip-flops 3 and 7, respectively, are low level. The signals 107 and 110 are connected to the bus 111, and the signal level value thereof can be read by the CPU 8 via the bus 111.

In this state, the interrupt request signal 101
It is assumed that (see FIG. 2E) is an active level and is input as the first interrupt request. This active level interrupt request signal 101 is input as a high level signal 103 (see FIG. 2 (f)) to the R terminal of the D flip-flop 3 via the OR circuit 1 and the D System input to flip-flop 3
A signal 107 (see FIG. 2G) is output at a high level from the D flip-flop 3 in synchronization with the rising edge of the clock 102 (see FIG. 2D). Signal 1
07 is input to the AND circuit 4 and the OR circuit 1
Is also fed back to and is also connected to the bus 111. In the AND circuit 4, the high level interrupt request signal 101 and the high level signal 107 output from the D flip-flop 3 are logically ANDed and output, and the high level output signal is an OR circuit. Input to 5. The signal 110 (see FIG. 2 (i)) output from the D flip-flop 7 is also input to the OR circuit 5, and the output signal 108 (see FIG. 2 (h)) is D.
The signal is input to the D terminal of the flip-flop 7. As described above, the signal 10 at the high level from the D flip-flop 3 is
When 7 is output, D flip-flop 7
The output signal 110 is in the low level state. As described above, the interrupt acceptance signal 105 is held at the high level. Therefore, at this time, the interrupt request processing for the CPU 8 by the first interrupt request signal 101 remains suspended. There is. These signals 107 (high level) and signal 1
The value of 10 (low level) is CP via the bus 111.
It can be read by U8, and the CPU 8 can refer to the values of these signals to confirm by the program that there is one interrupt request and that the interrupt request is pending. .

When the interrupt request signal 101 is generated again while the above interrupt processing is suspended,
This second active level interrupt request signal 10
The signal 108 output from the OR circuit 5 and input to the D flip-flop 7 in response to the input of 1 becomes high level in synchronization with the interrupt request signal 101, and thus is output from the D flip-flop 7. Signal 110
Is output at a high level in synchronization with the rise of the system clock 102. In this state,
The D flip-flop 3 is held in the set state, and the signal 107 output from the D flip-flop 3 is at the high level like the signal 110 output from the D flip-flop 7. . That is, D
Signals 107 and D output from flip-flop 3
The signals 110 output from the flip-flops 7 are both at high level. These signals 107 (high
The value of the level) and the value of the signal 110 (high level) can be read by the CPU 8 via the bus 111. By referring to the values of these signals, the CPU 8 has two interrupt requests. Moreover, it is possible to confirm by the program that the interrupt requests are both held.

As described above, when the interrupt request corresponding to the first interrupt request signal 101 is received once at the time when the interrupt request is made twice and the interrupt requests are both held. The interrupt acceptance signal 105 (see FIG. 2B) becomes low level and is input to the AND circuit 2. Therefore, the reset signal 106 output from the AND circuit 2 and input to the D flip-flop 3 becomes low level, whereby the D
Only the flip-flop 3 is reset, and the signal 107 output from the D flip-flop 3 changes to low level.
Level, and the D flip-flop 7 is still held in the set state.
The output signal 110 is kept at the high level. That is, the signal 107 output from the D flip-flop 3 is low level, and the signal 110 output from the D flip-flop 7 is high level.
These signals 107 (low level) and signals 110
The (high level) value is sent to the CPU 8 via the bus 111.
Can be read by
By referring to the values of these signals, there are two interrupt requests, and the first interrupt request is accepted,
The program can confirm that the second interrupt request is pending.

As described above, when the D flip-flop 3 is reset and the output signal 107 is low level, only the D flip-flop 7 is set and the output signal 110 becomes high level. The interrupt request signal 101 as the third interrupt request
In the same manner as described above, the signal 107 output from the D flip-flop 3 changes to the high level in synchronization with the rising of the system clock 102, and both the D flip-flops 3 and 7 Both the signals 107 and 110 output by the high level signal become high level. In this state, these signals 107 (high
The value of the level) and the value of the signal 110 (high level) can be read by the CPU 8 via the bus 111. In the CPU 8, the progress of the interrupt request / interrupt acceptance before the present time and these signals 107 and By referring to the value of 110, it can be confirmed by the program that there are three interrupt requests, only the first interrupt request is accepted, and the second and subsequent interrupt requests are suspended.

That is, by providing interrupt count storage means including a D flip-flop in cascade connection corresponding to the input of the interrupt request signal 101, the output values of these interrupt count storage means are read out to perform processing. It can be confirmed whether or not the interrupt process to be performed is missing. As the resetting operation against <br/> the D flip-flop 7 in the above state, a software reset signal (reset signal 109), and it is possible to reset only by a hardware reset signal. AND circuit 2 and AND as the hardware reset signal
Reset signal 104 for circuit 6 (see FIG. 2 (a))
, Is output from the AND circuit 2 and D
Reset signal 106 input to flip-flop 3
(See FIG. 2B) becomes low level, and AND
The reset signal output from the circuit 6 and input to the D flip-flop 7 also becomes low level, and the values of the signals 107 and 110 output from the D flip-flop 3 and the D flip-flop 7 are both low. It is output as level.

FIG. 3 is a block diagram showing a second invention of the present invention. As shown in FIG. 3, in this embodiment, the C which is the target of the interrupt processing request by the interrupt request signal 112.
Corresponding to the PU 19, the OR circuit 9 and the D flip-flop 11 that function as a first interrupt request count storage unit.
And an AN functioning as a second interrupt request count storage means
D circuit 12, OR circuit 13, and D flip-flop 1
5 and A that functions as a third interrupt request count storage means
An ND circuit 16, an OR circuit 17, a D flip-flop 18, and AND circuits 10 and 14 related to the reset function are provided. As is clear from the comparison with FIG. 1, in the present embodiment, the AND circuit 16, OR
Third interrupt request count storage means including a circuit 17 and a D flip-flop 18 is newly added.

In FIG. 3, the operations related to the D flip-flops 11 and 15 are similar to the operations of the D flip-flops 3 and 5 in the first embodiment, respectively, and the operation of the D flip-flop 18 is the same as that of the first embodiment. Since the operation is the same as that of the D flip-flop 5 in the first embodiment, detailed description thereof will be omitted. In the present embodiment, for example, as described in the first embodiment, the D flip-flop 1 is input by the second input of the interrupt request signal 112 while the interrupt processing is suspended.
In the state where the signal 118 output from 1 and the signal 121 output from the D flip-flop 15 are both at the high level, the interrupt request signal 112 is generated again in response to the third interrupt request. OR circuit 9
In response to this input, the D flip-flop 18 is set and the signal 123 output from the D flip-flop 18 goes high. Therefore, in this state, the values of the signals 118, 121 and 123 output from the D flip-flop 11, the D flip-flop 15 and the D flip-flop 18, respectively, are held at the high level. The value of the signal 118 (high level), the value of the signal 121 (high level) and the value of the signal 124 (high level) can be read by the CPU 8 via the bus 111. By referring to the values of these signals, the program can confirm that there are three interrupt requests and that the interrupt requests are both held.

In the above state, when the interrupt processing corresponding to the first interrupt request signal 112 is accepted once, the interrupt acceptance signal 116 becomes low level and is input to the AND circuit 10. Therefore, the reset signal 117 output from the AND circuit 10 and input to the D flip-flop 11 becomes low level, whereby only the D flip-flop 11 is reset and the signal 118 output from the D flip-flop 11 is reset.
Changes to a low level, and D flip-flop 15 and D flip-flop 18 are still held in their set state, so their output signals 121 and 123 remain high. Is held. That is, the signal 118 output from the D flip-flop 11 becomes low level, and the D flip-flop 15 and the D flip-flop 18 respectively.
The output signals 121 and 124 are at high level. These signal 118 (low level) value, signal 121 (high level) value and signal 123
The (high level) value is sent to the CPU 8 via the bus 111.
Can be read by
By referring to the values of these signals, there are three interrupt requests, and the first interrupt request is accepted,
The program can confirm that the third interrupt request and the third interrupt request are pending.

That is, in response to the input of the interrupt request signal 112, interrupt number storage means including D flip-flops are provided in cascade connection, and the output values of these interrupt number storage means are read out to perform processing. It can be confirmed whether or not the interrupt process to be performed is missing. In the present embodiment, as compared with the case of the first embodiment, by increasing the interrupt count storage means by one, the CPU 19 can confirm the number of interrupt request counts on the program by that amount. Increase. Therefore, by increasing the number of interrupt request number storage means including the D flip-flop, the CPU 19 gradually increases the number of interrupt requests that can be confirmed on the program, thereby executing the interrupt process corresponding to the interrupt request. There is an advantage that it becomes easier to confirm the presence or absence of a dropout.

Further, the D flip-flop 9 can be reset by the interrupt acceptance signal 116 or the hardware reset (reset signal 115), and the D flip-flop 15 and the D flip-flop 18 can be reset. Only possible with a software reset signal (reset signal 120) or a hardware reset signal (reset signal 115). As a hardware reset signal, the reset signal 115 is sent to the AND circuit 10 and the AND circuit 14.
Is input, the reset signal 11 output from the AND circuit 10 and input to the D flip-flop 11 is input.
7 becomes low level, and the reset signal output from the AND circuit 14 and input to the D flip-flops 15 and 18 also becomes low level, and these D flip-flop 11, D flip-flop 15 and D flip-flop 18 are all reset and the signals 118, 121 and 1 output from each D flip-flop are
The values of 23 are both low level.

[0023]

As described above, according to the present invention, in response to the input of an interrupt request signal, a circuit is provided by cascade-connecting a plurality of interrupt request number storage means for sequentially storing the input number of the interrupt signal. By configuring and reading the output value of each of the interrupt request number storage means by the CPU, it becomes possible to very easily confirm whether or not the interrupt processing execution to be processed is missing in the CPU, and the predetermined program is executed. This has the effect of significantly improving the debugging efficiency of.

Further, as the circuit for storing the number of interrupt requests, the circuit is constituted by a logic circuit including a flip-flop, so that the number of circuit components required for generating the interrupt request is smaller than that in the case of using a counter which has been conventionally used. There is an effect that the number of times can be confirmed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart in the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

1, 5, 9, 13, 17, 25-27, 36-40
OR circuits 2, 4, 6, 10, 12, 14, 16, 31-35, 4
1-43 AND circuit 3,7,11,15,18 D flip-flop 8,19,44 CPU 20 Interrupt request flag 21-23 Interrupt request counter 24 Priority control part 28-30 Latch 101,112,134 Interrupt request signal 102, 113 system clock 103, 107, 108, 110, 114, 118, 1
19, 121-123 signals 104, 106, 109, 115, 117, 120
Reset signal 105, 116 Interrupt acceptance signal 111, 124, 142 Bus 125-127 Request signal 128-130 Upper level request signal 131-133 Lower level request signal 135 Interrupt acknowledge signal 136-138 Selection signal 139-041 Counter decrement signal

Claims (2)

(57) [Claims] 1. An interrupt processing method for receiving an interrupt request signal for an information processing device executing program processing, and executing the interrupt processing during a predetermined interrupt processing reception period. Corresponding to the input of the first interrupt request signal, storing a predetermined level value for determining the occurrence of the first interrupt request signal, outputting a first signal corresponding to the predetermined level value, and During the interrupt processing acceptance period, in response to the input of the first interrupt request signal, an interrupt acceptance signal of a predetermined level
Calling of the predetermined level value inverts the interrupt request signal by
A first interrupt occurrence number storage means for storing the fact that there is no life and outputting a first signal corresponding to the inversion level value; and the i-th (i = 1, 2, 3, ... When connected to the interrupt generation number storage means of 1) in series, the i-th interrupt is generated outside the acceptance period of the interrupt processing.
The number of occurrences of the interrupt request signal has already been recorded in the number-of-times storing means.
In the case of being remembered, in response to the input of the [i + 1] th interrupt request signal, a predetermined level value for determining the occurrence of the [i + 1] th interrupt request signal is stored and corresponds to the predetermined level value. While outputting the [i + 1] th signal,
Within the acceptance period of the interrupt processing, the [i +
1] In response to the input of the interrupt request signal, the predetermined level value is inverted and stored via the interrupt reception signal of the predetermined level, and the [i + 1] th signal corresponding to the inverted level value is output. [I + 1] interrupt generation frequency storage means, and at least the interrupt level request / acceptance process can be confirmed by referring to the storage level value in the i-th interrupt generation frequency storage means. Characteristic interrupt processing method. 2. The first interrupt occurrence count storage means,
A logical sum circuit for inputting the interrupt request signal and a predetermined first feedback signal to perform a logical sum operation and outputting, and an output signal of the logical sum circuit and a system clock are input to the system clock. Outputs the first signal in synchronization with the interrupt acceptance signal or reset signal.
Can be reset, it is constituted by a flip-flop circuit further inputs the first signal to the OR circuit as the first feedback signal, interrupt occurrence count memory means of the first [i + 1] A logical product circuit for inputting the interrupt request signal and the i-th signal output from the i-th interrupt occurrence number storage means to perform a logical product operation and outputting; and an output signal of the logical product circuit and a predetermined signal. An OR circuit for inputting the i-th feedback signal, performing an OR operation, and outputting, and an output signal of the OR circuit and a system clock, and synchronizing with the system clock, the i-th signal And an interrupt acceptance signal or a reset signal
It makes it possible to reset the output, further interrupt processing method of the claim 1, wherein configured with a flip-flop circuit for inputting to the OR circuit a signal of the i as a feedback signal of the i-th.