JPS6336545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lock control system, and more particularly, the present invention relates to a lock control method, in which a plurality of processors normally share shared resources including hardware such as input/output devices, buses, and data buffers, and software such as programs and data. The present invention relates to a lock control system for a lock operation performed to execute exclusive control in a multiprocessor system that operates as one system as a whole while performing exclusive control exclusively occupied by a single processor.

When multiple resource requesters such as processors request one shared resource in an asynchronous state, exclusive control is required to avoid conflicting requests by each resource requester and control them without contradiction. A lock that grants the right to use a shared resource to one normal processor and processes data while excluding its use by other processors.
The operation is well known.

In conventional multiprocessor systems, each processor that requires the right to use a shared resource issues a lock request at will. Therefore, if another processor has already issued a lock request, been given the right to use the shared resource, and is executing data processing, the lock request will fail. In conventional multiprocessor systems, if a lock request fails, the processor either waits for the lock to be released and repeats the lock request until the lock request succeeds, or the lock is in use and access to subsequent locks is allowed. Either method was used.

According to the former method, the processor can recognize that a lock request has failed, so it can utilize waiting time by executing external event processing that does not require a lock, or by counting the frequency of lock failures. Since there are many lock requests that are available but fail, there is a drawback that the responsiveness to lock requests deteriorates as the number of processors increases.

The disadvantage of the latter method is that access to a lock request while the lock is in use is prohibited and the response remains unchanged, so the processor cannot process other external events and therefore cannot make effective use of waiting time. There is.

Note that as a variation of the latter method, access may be permitted after confirming that the shared resource is not in use, but in this case as well, access is prohibited from the processor's perspective until the lock is successful. The processor is placed in a waiting state, and the processor itself cannot essentially recognize that the lock has failed, so the disadvantage is that the waiting time cannot be used effectively.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to perform lock requests for exclusive control of shared resources in a multiprocessor system.If the lock request by the own processor fails, the other processors executing the process can be It has a means of not issuing a lock request until a lock release notification is received from the controller, which eliminates meaningless operations that continue to cause lock requests to fail, and greatly reduces the deterioration in processing performance of multiprocessor systems. The object of the present invention is to provide a lock control method.

The method of the present invention, in a multiprocessor system that performs exclusive control of system shared resources by locking, is capable of locking in response to a lock request from a plurality of processors that make up the multiprocessor system. a lock request result notifying means for notifying each processor of a successful or unsuccessful lock result depending on whether the lock is successful or not, and causing the processor to execute a process corresponding to the result; A lock request failure recognition means is provided, in which the processor that made the lock request recognizes when the request fails, and a processor other than the own processor recognizes that the processor that made the lock request succeeds in the lock request and executes the processing to be performed. a lock release notification means for notifying all of the plurality of processors of the lock release of the lock; and a lock release notification means for notifying all of the plurality of processors of the lock request failure, and when the processor that issued the lock request recognizes the failure of the lock request by the lock request failure recognition means, the lock release means A lock request suppressing means for suppressing a lock request until notification of lock release is received from another processor; and a lock request failure recognition means, when the processor that issued the lock request recognizes the failure of the lock request, the lock request result is determined. and lock request result changing means for changing the result of the notification means.

Next, the present invention will be explained in detail with reference to the drawings.
Referring to FIG. 1, one embodiment of the present invention operates as a plurality of processors constituting a plurality of processor systems constituting a multiprocessor system.
It is composed of a CPU (0) 1, a CPU (1) 2, and a lock control circuit 3.

In the embodiment shown in FIG. 1, two CPUs, CPU(0)1 and CPU(1)2, are shown as processors, but any number of CPUs may be used.

CPU (0) 1 and CPU (1) 2 are CPUs having the same configuration, and as shown in CPU (0) 1, a selector 10, a flip-flop circuit 11, OR circuits 12, 20, a flip-flop circuit 13, and an AND circuit.
Circuit 14, NOT circuit 15, 16, AND circuit 1
7, and flip-flop circuits 18 and 19, as well as a control memory 21, a control memory address register 22, and a control memory register 23 as components included in the microprogrammed CPU.
It is composed of the following.

Now, the control memory 21 that stores and stores microprograms reads out the microprogram designated by the control memory address signal received from the control memory address register 22 via the output line 221, and transfers it via the output line 211 to the control memory address register 22. Send on 23rd. The microprogram stored in the storage control register 23 includes a lock control field that specifies whether a lock is required, and when a lock request is specified by this lock control field, the lock request is specified in this lock control field 23a. The contents of the microprogram are sent as a lock request signal to the selector 10 via the output line 231, and the contents of the microprogram are output via the output line 232, and after being decoded by a decoder etc., the execution of the contents is controlled. The data is supplied to an execution control unit (not shown) etc. that performs the processing. Processing specified by the microprogram is executed via this execution control unit, and then the next microprogram is executed once again in the control storage address register 22.
The microprograms in the control memory 21 are executed one after the other as specified by.

The lock request signal thus supplied and a lock non-request signal input through the input line 101 and specifying the content of not requesting lock are applied to the selector 10, and the output line 131 is output from the flip-flop circuit 13, which will be described later. When the select signal supplied via the lock is applied, the lock non-request signal is selected, and when the select signal is not supplied, the lock request signal is selected and sent to the lock control circuit 3 via the output line 102. The above-mentioned lock non-request signal is issued regardless of whether or not the lock request signal is input when another CPU, for example CPU (1), has successfully requested a lock and is executing a process and it is inappropriate to issue a lock request. This signal is selected in place of the lock request signal and sent to the lock control circuit 3 via the output line 102, and is set as a prespecified code signal having a content that does not make a lock request.

In the conventional lock request method, only the lock request signal is repeatedly output from each CPU without providing these two operating states of lock request and lock non-request, which causes the above-mentioned drawbacks. becomes.

Therefore, in the present invention, this drawback is eliminated as follows.

In order to avoid meaningless lock requests, a processor that has once failed in a lock request must be able to recognize that the ability to successfully request a lock has occurred, that is, that another processor that was holding the lock has lost the lock. It won't happen.

CPU (0) 1 and CPU (1) 2 each send microprogram instructions read from the control storage register 23 and decoded via a decoder etc. to the aforementioned execution control unit, and the instructions are executed while being controlled by this unit. However, the lock can also be released by CPU(0)1 or CPU(1).
The CPUs of the second class are set in advance to notify each other at this stage of execution control.
In the embodiment shown in the figure, when the lock state by CPU(1)2 is released, the input line 11 from CPU(1)2 is released.
Microprogram instruction processing is performed by the control memory 21, the control memory address register 22, the control memory register 23, etc. such that a binary logic value "1" level signal is sent to the flip-flop circuit 11 as an unlock signal via the The input to the flip-flop circuit 11 is determined through the .

Like the flip-flop circuits 13, 18, and 19, the flip-flop circuit 11 changes the input logic value to "1" or "0" each time the clock signal CL is applied.
This is a so-called D-type flip-flop circuit that obtains output logic values "1" and "0" in response to the output voltage.

When the flip-flop circuit 11 is unlocked by the CPU (1) 2, it is set by the lock release signal and outputs a logic value "1" level, which is sent as one input of the OR circuit 12 via the output line 112. Send.

When an interrupt to CPU (0) 1 occurs due to an external event via an input line 222 to the OR circuit 12, the interrupt is sent to the control memory 21 via the control memory address register 22, and the OR circuit 12 A logic value "1" level signal supplied as another input is input as an external event signal.

Therefore, when either of these two inputs is supplied at the logic "1" level, the OR circuit 12 outputs a signal at the logic "1" level and sends this to the output line 1.
21 to the flip-flop circuit 13 as a reset signal, and when neither of the two inputs is supplied and therefore the lock continues, the flip-flop circuit 13 does not send out a reset signal.

Now, the lock request signal sent out via the output line 102 in response to a lock request from the microprogram of CPU (0) is sent to the lock control circuit 3. All the lock request signals from other CPUs are also input, and each time the lock control circuit 3 receives these inputs, it outputs a reply signal with a logical value of "1" level meaning a response to this lock request signal. is sent to the AND circuit 14 and flip-flop circuit 19 via the output line 301, and at the same time, the input states of all lock request signals at that time are judged, and if there is a lock request signal that has already been successfully locked, the logic value is set to "0" level. , if no other lock request signal is input, a signal of logical value "1" level is sent to the NOT circuit 15 and the AND circuit 17 via the output line 302 as a lock failure signal and a lock success signal, respectively.

When the lock control circuit 3 outputs a lock failure signal, that is, a signal with a logic value "0" level,
This is converted to a logical "1" level by NOT circuit 15 and supplied to flip-flop circuit 13 via output line 151. On the other hand, the reply signal at the logic value "1" level is supplied to the AND circuit 14, and the AND circuit 14 receives this and the clock signal CL.
When receiving two inputs at the same time, the clock signal CL is output to the output line, and a clock signal with a logic value of "1" level is applied to the clock terminal of the flip-flop circuit 13, and the output of the NOT circuit 15 is set at the timing of this clock signal. It is latched as a signal and generates a logic value "1" level as an output, which is sent to the selector 10 as a selector signal via an output line 131.

In response to this selector signal, selector 10 converts a lock non-request signal input via input line 101 into a lock request signal and sends it to lock control circuit 3 via output line 102.

In this way, if the lock request is unsuccessful, the failure of the lock request is recognized and subsequent lock requests are suppressed. However, as described above, if the flip-flop circuit 11 receives a lock release signal via the output line 111, Alternatively, when an external event signal is received via the output line 222 and a reset signal with a logic value "1" level is input from the OR circuit 12 to the flip-flop circuit 13, the flip-flop circuit 13 is reset, and the output line 131 receives a logic value "0". ``level is output, so that the sending of the lock non-request signal is stopped and the lock request signal is sent to the lock control circuit 3 via the output line 102.

The lock control circuit 3 receives the lock request signal in this state, and if the lock request fails, repeats the above-mentioned operation, and if the lock request is successful, outputs a signal of logical value "1" level via the output line 302 as a lock success signal. Send as. In this case, the flip-flop circuit 13 receives the logic value "0" level and sends an output of the logic value "0" level to the output line 131, so that the selector 10 does not switch between the lock request signal and the lock non-request signal. do not have.

In this way, if the lock request is unsuccessful, it is recognized and the lock request is suppressed until the lock release signal is input, and if the lock is successful after receiving the lock release signal, the CPU (0 ) 1 is executed, and when this is completed, CPU (0) 1 to CPU (1) 2
A lock release signal is notified to other CPUs such as the CPU, and this operation is performed as follows.

That is, if the lock request is unsuccessful, the logic value "1" is also input to the NOT circuit 16 as the output of the flip-flop circuit 13 via the output line 131, and this is also input to the NOT circuit 16 as a logic value "0" level via the output line 161. and is sent out as one input of the AND circuit 17. AND circuit 17 has output line 3
02 is added as another input, but in this case the AND condition is not successful and a logic "0" level is output on the output line 171.

If the lock request is successful, the above-mentioned logic value level is reversed, and a signal with a logic value "1" level is applied to each of the two inputs of the AND circuit 17. Therefore, the AND condition is established and the output line 171
A signal with a logic value "1" level is supplied to.

The flip-flop circuit 18 receives a clock signal.
Each time CL is applied, a logic value of "0" or "1" level corresponding to the logic value of this input is outputted, and this is outputted via the output line 181, under the control of the execution control section described above. The address of the next microprogram instruction to be executed specified by the control storage register 23 is changed and the output of the flip-flop circuit 18, i.e., lock success or failure, is changed as specified by the control storage address register 22. The processing of the microprogram instruction corresponding to is executed.

On the other hand, each time a lock request signal is input to the lock control circuit 3, a reply signal having a logic value of "1" level is input to the flip-flop circuit 19 via an output line 301. This reply signal is output as a signal in response to the lock request signal when the signal input to the lock control circuit 3 via the output line 102 is a lock request signal, and is output from the flip-flop circuit 13 via the output line 131. When the output signal takes the logical value "0", that is, when the flip-flop circuit 13 is receiving the lock release signal via the output line 121, the lock request by the input lock request signal is not activated by the lock control circuit. The state of success or failure based on the determination in step 3 is possible only when this reply signal is output. When a reply signal having such a meaning is supplied to the flip-flop circuit 19, it is set every time the clock signal CL is applied, and outputs a logical "1" level output to the output line. In this way, the flip-flop circuit 19 also outputs a logical value of "1" or "0" in response to the input of the reply signal, and this is used as information to wait for either the success or failure of the lock request by the flip-flop circuit 18. After being outputted to the output line 191, the control storage register 23 changes the specified next microinstruction address in exactly the same way as the output of the flip-flop circuit 18, and locks the address specified by the control storage address register 22 successfully or unsuccessfully. Specifies the next microprogram to be executed in response to the process, and causes the process to be executed.

If the lock request is unsuccessful, the processor will continue to
As mentioned above, the output line 131 has a logical value “1”.
As a result, the AND circuit 17 outputs the logical value "0", the OR circuit 20 outputs the logical value "1", and the outputs of the flip-flop circuits 18 and 19 are the logical value "0" and the logical value, respectively. “1”
will be changed to This is equivalent to the result of an unsuccessful lock request, and the microinstruction address is specified to point to the microinstruction address that causes the lock failure to occur.

Furthermore, if the lock request is successful, or if the lock request is unsuccessful and a lock release notification is generated from another processor, or after an external event occurs, the output line 131 will have a logic value of "0". Output flip-flop circuit 1
8 and 19, the output of the lock control circuit 3 is stored as is.

In this way, when the lock is released, lock requests from multiple CPUs are received and judged, and success or failure of the lock is determined by each CPU along with a reply signal in response to the lock request.
The result of the lock request is notified so that the successful CPU executes the original processing, and the unsuccessful CPU is placed in a waiting state that suppresses the meaningless repetition of lock requests and is given a chance for the next successful lock request. A highly effective lock operation is achieved by means of a lock request result notifying means and a lock request result changing means which notifies the CPU and causes the CPU to execute processing corresponding to the result.

The lock control method of the present invention is such that in a multiprocessor system that performs exclusive control of system-shared resources by locking, a processor that has failed in a lock request recognizes this and avoids meaningless repeated requests until the lock is released. In addition, the basic feature is that when a processor that has successfully made a lock request has completed its processing task, it notifies other processors of the lock release and controls them to issue a lock request. , various modifications of the embodiment shown in FIG. 1 are possible.

For example, in the embodiment of FIG.
This example uses two CPUs, CPU(0)1 and CPU(1))2, but the number can be set arbitrarily depending on the scale of the Matsuchi processor system and the same implementation can be performed. is clear.

In addition, flip-flop circuits 11, 13, 1
8 and 19 are D-type flip-flop circuits, but these may be replaced with other flip-flop circuits having equivalent functions, and any of the above can be easily implemented without detracting from the spirit of the present invention. It is something that can be used.

As explained above, according to the present invention, in a match processor system that performs processing while performing exclusive control of system shared resources by locking,
When a lock request fails, it recognizes this and repeatedly suppresses the lock request until it receives a lock release signal that enables the lock, and when the lock is successful and the original principle has been completed, the lock release signal is sent to another lock request. By providing a means for notifying all processors in a multiprocessor, it is possible to realize a lock control method that avoids meaningless repetition of lock requests and can greatly improve the deterioration in system performance of a multiprocessor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1, 2...CPU, 3...Lock control circuit, 1
1, 13, 18, 19... flip-flop circuit, 12, 20... OR circuit, 14, 17...
AND circuit, 15, 16...NOT circuit, 21...
Control memory, 22...Control memory address register,
23...Control storage register.

Claims (1)

[Claims] 1. In a multiprocessor system that performs exclusive control of system-shared resources by locking, when a lock request is received from multiple processors that make up this multiprocessor system, it is possible to respond to the lock request and determine whether locking is possible or not. a lock request result notifying means for notifying each processor of a lock success or failure result depending on the lock request and causing the processor to execute a process corresponding to the result; A lock request failure recognition means that the processor that made the lock request recognizes when the lock request fails; A lock release notifying means for notifying a processor of lock release, and a lock request failure recognition means that when the processor that issued the lock request recognizes the failure of the lock request, the lock release means releases the lock from another processor. A lock request suppressing means for suppressing a lock request until a lock request is notified of cancellation, and a lock request failure recognition means for detecting the result of the lock request result notification means when the processor that issued the lock request recognizes the failure of the lock request. 1. A lock control system comprising: a lock request result changing means for changing a lock request result; and controlling a lock request in a multiprocessor system.