JPS59173866A - Lock control system - Google Patents

Abstract

PURPOSE:To prevent the performance deterioration of a multi-processor by recognizing the failure of a lock request, if occurs, to avoid the repetition of useless lock requests. CONSTITUTION:A lock control system consists of CPUs 1 and 2 which serve as plural processors and a lock control circuit 3. The CPU1 and 2 send a microprogram instruction which is read out of a control storage register 23 and decoded to an execution control part. The circuit 3 recognizes the failure of a lock request, if occurs, and resets a flip-flop 13. Thus the lock request is suppressed repetitively until a lock release signal which gives a lock enable state is received. When a lock request is accepted, a logic ''0'' is delivered to an output line 131. At the same time, the output of the circuit 3 is stored as it is in flip- flop circuits 18 and 19.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lock control system, and in particular, the present invention relates to a lock control system in which multiple processors normally share shared resources, including hardware such as input/output devices, buses, and data buffers, and software such as programs and data, to a single processor. The present invention relates to a lock control method for a lock operation performed to execute exclusive control in a multi-grocer system that operates as one system while performing exclusive control exclusively for exclusive use.

When multiple resource requesters such as processors request all of one shared resource in an asynchronous state, exclusive control is required to avoid conflicting requests from each resource requestor and to control them without contradiction. Locking (Lock), which normally grants full usage rights to shared resources to one processor through exclusive control and executes data processing while excluding usage by other processors.
ock) operation is well known.

In a conventional multiprocessor system, each processor that requires the right to use a shared resource issues a lock request at will. Therefore, if another processor has already issued a lock request and been given the right to use the shared resource and is processing data, the lock request will fail, and the lock request will continue to be made repeatedly until the lock request succeeds. After the lock request is successful, the processing by that processor will be executed.

-However, such lock requests are made by all processors that make up the multiprocessor system.
Since it is possible to do this repeatedly, the 7-system operation of the entire multiprocessor system is affected by repeated lock requests as described above, and the processing performance of all processors is also significantly reduced in proportion to the number of them. There is.

An object of the present invention is to eliminate the above-mentioned drawbacks, and in a lock request for exclusive control of a shared resource in a multiprocessor system, if the lock request by the own processor fails, the lock is successful and the other processors executing the process Is it a method of not issuing a lock request until a lock release notice is received, which is a pointless action that keeps the lock request failing? An object of the present invention is to provide a lock control method that can eliminate and significantly reduce deterioration in processing performance of a multiprocessor system.

In a multiprocessor system in which all system shared resources are exclusively controlled by locking, the system of the present invention is capable of determining whether locking is possible or not in response to a lock request from a plurality of processors that make up the multiprocessor system. lock request result notification means for notifying all the processors of a result of lock success or failure depending on whether the lock is possible and causing them to execute processing corresponding to the result; When the lock request fails, the lock request failure recognition means is recognized by the processor that made the full lock request, and after the processor that made the lock request has succeeded in the lock request and executed the necessary processing, the self-processor lock release notification means for notifying all of the plurality of processors other than the processors of the lock release, and when the processor that issued the lock request recognizes the failure of the lock request by the lock request failure recognition means, the lock release means sends a lock release notification to the other processors. a lock request suppressing means for suppressing lock requests from n7) to notification of lock release, and a result of the lock request result notifying means when the processor that issued all the lock requests recognizes the failure of the lock request by the lock request failure recognition means. '(i--consisting of means for changing the lock request result.

Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes CPU(0)1. C
PUα) 2 and a lock control circuit 3.

In the embodiment of FIG. 1, as a processor (7)
CPU, 2 CPU, (0) 1 and CPU (1) 2
Although 2 pieces are shown on the gold side, there is no problem even if there are 2 pieces on the gold side.

CPU(o)1 and CPU(1)2 are CPUs having the same configuration, and as shown in CPU(0)1, a selector 10° flip-flop circuit 11. OR circuit 12
,20. Flip-frog circuit 13. AND circuit 14.
NO ground 1516, AND circuit 17. In addition to flip-flop circuits 18 and 19, control memory 2 is a component included in the microprogrammed CPU.
1 degree control storage address register 22, control storage register 23, etc.

Now, control memory 2 that stores and memorizes microprograms.
1 is the output line/2 from the control storage address register 22.
'211 The microprogram specified by the control storage address signal received via the output line is read out; '211
The microprogram stored in the control storage register 23 includes a lock control field for specifying a lock request. When a request is specified, the contents specified in the lock control field 23 (a) are sent as a lock request signal to the selector 1o via the output 2 ear 231e, and the contents of this microprogram are sent to the output line 232. After being decoded by a decoder etc., it is supplied to an execution control unit (not shown) that controls the execution of the contents. A process is executed, and then the next microprogram is again specified by the control memory address register 22, and so on, and the microprograms in the control memory 21 are executed one after another.

The lock request signal thus supplied and a lock non-request signal input through the input line 101e and instructing the content not to request lock are applied to the selector 10, and the lock request signal is input from the flip-flop circuit 13, which will be described later. When the select signal supplied via the output line 131 is applied, the lock non-request signal is selected, and when the select signal is not supplied, the lock request signal is selected. Send to 3. The above-mentioned lock non-request signal is sent regardless of whether or not the lock request signal is input when another CPU, for example CPU (1), has successfully requested a lock and is executing a process and it is inappropriate to make a lock request. This signal is set in advance as a specific code signal that has the content that no lock request is made.

In the conventional lock request method, only the lock request signal is repeatedly output from each CPU without providing the two operating states of lock request and lock non-request, and this results in the above-mentioned drawbacks. It happens.

Therefore, in the present invention, this drawback is eliminated as follows.

In order to avoid meaningless lock request fees, a processor that has once failed in a lock request must not be able to recognize that there is a possibility that the lock request will succeed, or that another processor that was holding the lock has released the lock. Must not be.

CPU(o)1 and CPU(1)2 are each read from the control storage register 23 and decoded via a decoder or the like.
The microprogram instructions are sent to the above-mentioned execution control unit, and the instructions are executed while being controlled by this unit.However, unlocking is also performed by each CPU such as CPU (0) 1 and CPU α) 2.
In the embodiment shown in FIG. 1, the CPU (1) 2
When the lock state is released by CPU (1)
2 through the input line 111t'', a binary logical value “1”
level signal is sent to the flip-flop circuit 11 as a lock release signal to the control memory 21. The control storage address register 22, control storage register 23, etc. perform microprogram instruction processing to
The input of the 21 circuit 11 has been determined.

The flip-flop circuit 11 is the flip-flop circuit 1
Similar to 3.18 and 19, this is a so-called D-flip-flop circuit that obtains an output logical value of 11'' in response to an input logical value of ``1'' or ``0'' every time the clock signal CL is applied. .

The flip-flop circuit 11 is output by the CPU (1) 2 as a single unit of the circuit 12.

If an interrupt to CPU(o)i is generated by an external event through an input signal 222t'' to the OR circuit 12, an interrupt is generated to the control memory 21 via the control memory address register 22. A signal at the logic value '1'' level, which is supplied as another input to the OR circuit 12, is input as an external event signal.

Therefore, the OR circuit 12 outputs a signal at the logic level "vrx" when one of these two inputs is supplied at the logic value "'1" level. The reset signal is supplied to the flip-flop circuit 13 as a reset signal (fN), and when neither of the two input signals (i) is received and therefore the lock continues, no reset signal is sent to the flip-flop circuit 13 (n).

Now, the lock request signal sent out via the output line 102 in response to a lock request from the microprogram of CPU (0) is sent to the lock control circuit 3. All lock request signals from other CPUs such as
Every time it receives these inputs, it outputs a regri signal with a logical value of 1" level in response to this lock request signal, and sends this to the AND circuit 14 and the flip-flop circuit 19 via the output line 301. At the same time, the input states of all lock request signals at that time are judged, and if there is a lock request signal that has already been successfully locked, the logic value is "0" level, and if no other lock request signals are input.

In this case, a logic 11'' level signal is sent to NOT circuit 15 and ANN circuit 17 through output line 302 as a lock failure and lock success signal, respectively.

When the lock control circuit 3 outputs a lock failure signal, that is, a signal with a logic value of "0" level, this signal is converted to a logic value of "1" level by the NOT circuit 15 and then sent to the flip-flop via the output line y151r. The retry signal at the logic value '1'' level is supplied to the circuit 13.
When the AND circuit 14 simultaneously receives the two signals of this signal and the clock signal CL, it outputs the clock signal CL (, -) to the output line, and the clock signal with a logic value of 61'' level is output to the flip-flop circuit 13. At the timing of this clock signal, the output of the NOT circuit 15 is latched as a set signal, and the logical value "1#1# level" is applied to the clock terminal of fL. Send as.

Selector 10 selects input line 1 by this selector signal.
The lock non-request signal inputted through 01 is converted into a lock request signal and sent to the lock control circuit 3 through output line 102.

In this way, if the lock request is unsuccessful, the failure f of the lock request is recognized and subsequent lock requests are suppressed, but as described above, no lock release signal is sent to the flip-flop circuit 11 via the output line 111k. When the flip-flop circuit 13 receives the external event tH signal through the output signal 222k, or receives the external event tH signal from the OR circuit 12, the flip-flop circuit 13 is reset. Kaline 131
A logic 1ro'' level is output at n1, so the sending of the lock non-request signal is stopped, and a lock request signal is sent to the lock control circuit 3 via the output line 102.

If the lock control circuit 3 receives the lock request signal in this state, it repeats the above-mentioned operation if the lock request fails, and if the lock request is successful, it outputs a signal with a logic value @1'' level through the output line 302 indicating that the lock is successful. In this case, the flip-flop circuit 13 outputs the logic value “0#”.
In response to the level, an output with a logical value of ``'0# level'' is sent to the output line 131, so that the selector 10 does not switch between the lock request signal and the lock non-request signal.

In this way, if the lock request is unsuccessful,
All lock requests are suppressed until a lock release signal is input after recognizing the lock, and if locking is successful after receiving a lock release signal, the process specified by the microprogram in CPU (0) 1 is executed. When the file is completed, the CPU
(0) 1 notifies other CPUs such as CPU α) 2 of a lock release signal, and this operation is carried out as follows.

That is, if the lock request is unsuccessful, the logic value '1'' is output from the flip-flop circuit 13.
1' is also input to the NOT circuit 16, and this signal is sent out as a logical value "0" level through the output line 161k and the αD circuit 1701. A logic value "0" level is applied as another input to the AND circuit 17 via the output line 302, but in this case, the logic value "0" level is applied as another input.
ND The condition does not hold and the output line 171 has a logical value ""
0” level is output.

If the lock request is successful, the above-mentioned logic value level is reversed.A signal of the logic value "1" level is applied to the two inputs of the AND circuit 17, so the AND
When the condition is met, a signal with a logical value of "1" level is supplied to the output line 171.

The flip-flop circuit 18 outputs a logic value of 0'' or "1" level corresponding to the logic value of this input every time the clock signal CL is applied. Then, under the control of the above-mentioned execution control unit, etc., the address of the next microprogram instruction to be executed is changed as specified by the control storage register 23, and the flip-flop is specified by the control storage address register 22. Processing of microprogram instructions corresponding to the output of the circuit 18, ie, lock success or failure, is executed.

On the other hand, each time a lock request signal is input to the lock control circuit 3, a reply signal of logical value "1# level" is input to the flip-flop circuit 19 via all output lines 301. The reply signal is output line 10
When the signal input to the lock control circuit 3 via 2 is a lock request signal, there is a signal '11' which is output as a response to this lock request, and is a signal output from the flip-flop circuit 13 via the output line 131ft. If it takes the logic rOTt, that is, when the flip-flop circuit 13 is receiving the lock release signal via the output line /121', the lock request signal based on the input lock request signal is determined by the lock control circuit 3. Therefore, the state of success or failure is possible only when this reply signal is in the output state. When a reply signal having such a meaning is supplied to the flip-flop circuit 19, it sends out to the output line an output of n logic value "1" level, which is set every time the clock signal CL is applied.

In this way, the flip-flop circuit 19 also changes to the logic value ""1" or "O" depending on whether or not the reply signal is input.
” is output to the output line 191 as information to wait for whether the lock request by the flip-flop circuit 18 is successful or unsuccessful. After that, it is controlled in exactly the same way as the output of the flip-flop circuit 18. The next micro-instruction address specified by the memory register 23 is changed to the address specified by the control memory address register 22, and the next micro-program to be executed is specified in response to lock success or failure, and its processing is executed. Let it be carried out.

If the lock request is unsuccessful, the processor outputs the logic value ``1#'' to the output line /131 as described above, unless a lock release notification is generated from another processor or an external event occurs. As a result, the AND circuit 17 outputs a logical value of 0, the OR circuit 2o outputs a logical value of ``1'', and the outputs of the flip-flop circuits 18 and 19 each have a logical value of n''. '0'', and the logical value @1#. This n is equal to the result of an unsuccessful lock request, and the microinstruction address is specified to point to the microinstruction address that causes the lock failure to proceed.

Also, if the lock request is successful, or if the lock request is unsuccessful, the other processor?

After a lock release notification occurs and an external event occurs, the output line 131 has a logical value @
The output of the lock control circuit 3 is stored as it is in the flip-flop circuits 18 and 19.

In this way, in the unlocked state, multiple CP
Upon receiving the lock request from U, the CPU determines whether the lock was successful or not and sends a retry signal in response to the lock request to each CPU, and the successful CPU executes the original processing. An unsuccessful CPU
, the result of the lock request f: is notified to the CPU, and the CPU executes the process corresponding to this result in a standby state that suppresses the meaningless repetition of the lock request and gives all chances for the next successful lock. The lock request result notifying means and the lock request result changing means provide an extremely effective locking operation.

The lock control method of the present invention is such that in a multiprocessor system that uses locks to perform exclusive control of system-shared resources, a processor that has failed in a lock request recognizes this and makes meaningless repeated requests until the lock is released. The basic feature is that when a processor that has successfully made a lock request has completed its processing task, it notifies other processors of the lock release and controls them to make a lock request. Various modifications of the embodiment shown in FIG. 1 are possible.

For example, in the embodiment of FIG.
0) 1 oJ: and CPU (1) 2 no 2 pieces tJll f
, 6, case e' is taken as an example, but it is clear that this number can be arbitrarily set depending on the scale of the multiprocessor system O and the implementation can be carried out in exactly the same way.

Also, flip-flop circuits 11.13.18. and 19 is a D-type flip-flop circuit,
There is no problem in replacing these with other flip-flop circuits having equivalent functions, and the above can be easily implemented without detracting from the gist of the present invention.

As explained above, according to the present invention, in a multiprocessor system that performs processing while performing exclusive control of system-shared resources, when a lock request fails, this f'Lt-recognizes and locks possible state. The method of repeatedly suppressing lock requests until a lock release signal is received, and then notifying all other processors of the lock release signal when the lock is successfully completed and the original purpose is completed, is meaningless by distributing the money. Avoiding repeated lock requests has the effect of realizing a lock control scheme that can significantly improve the overall performance of a multiprocessor system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.4...CPU, 3...Lock control circuit, 11.13゜18.19...Flip-flop circuit, 12,20...OR circuit , 14
, 17...AND circuit, 15.16...
・NOT circuit, 21... Control memory, 22...
. . . Control storage address register, 23 . . . Control storage register. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a multiprocessor system that uses locks for exclusive control of system-shared resources, is it possible or impossible to lock in response to a lock request from multiple processors that make up this multiprocessor system? a lock request result notifying means for notifying each processor of a result of success or failure of the lock and causing the processor to execute a process corresponding to the result; When the lock request fails, f'Lf is recognized by the lock request failure recognition means recognized by the processor that made the lock request, and after the processor that made the lock request succeeds in the lock request and executes all the processing that should be carried out, the above-mentioned plurality of processors other than the own processor lock release notification means for notifying all processors of lock release; and when a processor that issued a lock request recognizes all failures of the lock request by the lock request failure recognition means, the lock release means requests unlocking from other processors. a lock request suppressing means for suppressing a lock request until a lock request is notified; and a lock request for changing a result of the lock request result notification means when a processor that has received a lock request by the lock request failure recognition means recognizes all failures of the lock request. 1. A lock control method comprising a result changing means to control lock requests in a multiprocessor system.