JP2011118756A - Exclusive control program, exclusive control method, and information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow more effective utilization of capability and performance of an information processing system. <P>SOLUTION: An information processing system 1 divides a memory 2 into a user space 10 and a kernel space 20 to manage them. Execution of a critical section in a user program 11 disposed in the user space 10 by one thread competes with another thread, a kernel program 21 uses a user space atomic access function 203 to atomically access a lock word (data for exclusive control) 100 disposed in the user space 10 and determines whether executing the critical section by the one thread is possible or not. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an exclusive control program, an exclusive control method, and an information processing system, and particularly to a technique for performing exclusive control when a critical path is executed by a plurality of threads.

  In an information processing system, a plurality of processes and threads are generally operated in parallel in order to efficiently use computer resources such as a processor.

  Processes and threads are similar concepts in that they mean execution units that execute programs. However, in general, a process is independent of other processes, and a memory space and a file for each process are separate. On the other hand, unlike processes, threads share memory space and files. To be precise, the accurate expression is that one or more threads exist in one process.

  A multi-process system has a configuration in which only one thread exists in one process, and a multi-thread system has a configuration in which a plurality of threads exist in one process. That is, in a multi-thread system, a plurality of threads belonging to one process execute the same program.

  In the following description, a unit for executing a program is expressed as a thread. However, when a different program or a different memory space is considered, it is expressed as a process.

  In an information processing system configured to operate a plurality of threads in parallel, execution of another process by another thread may interrupt at any time during the execution of one process by one thread. If there is no relationship between these processes, the result obtained even if another process interrupts during one process does not change and does not cause a problem.

  However, when there is a relationship between processes, if another process interrupts in the middle of one process, the result obtained is different, which may cause a problem.

  For example, it is assumed that two threads execute a process of adding “1” to the same variable (that is, a process of reading a variable from a memory or the like, adding “1”, and writing the result back to the memory or the like) in parallel. The problem in this example is that the processing by the other thread (processing that adds “1” to the variable) is interrupted between when one thread reads the variable and writes back the result of adding “1”. This is the case.

  When no interruption occurs, the two threads sequentially perform an operation of adding “1” to the variable, so that the value of the variable increases by “2”. This processing result is correct considering the contents of the processing performed by each thread.

  On the other hand, when an interrupt occurs, one thread writes back a value obtained by adding “1” to the value read by itself without sensing the update of the variable by the other thread. Accordingly, although the two threads perform an operation of adding “1” to the variable, the value of the variable only increases by “1”, and a correct processing result cannot be obtained.

  In this way, the processing section that causes a problem when interrupted by other processing in the middle of processing (in the above example, the section from reading the variable to writing back the result of addition) is called the critical section and interrupted by other processing. The exclusive control is not performed explicitly.

  If one processor is responsible for program execution, switching to other processing is prohibited when entering the critical section, and switching to other processing is permitted when exiting the critical section. Can be guaranteed not to interrupt. When there is one processor, the execution of another program (another process) interrupts while executing a certain program as a process because an event that triggers process switching occurs during the first process execution, and the operating system This is because (OS) performs process switching. Therefore, if you instruct the operating system to prohibit switching to another process (other process), even if some event that triggers process switching occurs in the process switching prohibited state, at that time It is possible to control to perform process switching when the first process permits switching to another process without performing process switching.

  On the other hand, in a multiprocessor system, a correct processing result cannot be guaranteed only by prohibiting switching to another process. This is because prohibition of switching to another process is effective for a processor executing the program (operating the other process), but does not affect program execution by the other processor.

  Generally, an exclusive control for preventing program execution by another processor from entering a critical section is a flag indicating whether or not there is a process executing the critical section (hereinafter, lock word). ) Is used. In the following description, the right to execute a critical section (right to enter a critical section) may be referred to as “lock”.

Specifically, each process confirms the lock word when entering the critical section, and executes the processing shown in (1) or (2) below.
(1) If the lock word is “value indicating unused (hereinafter, unlocked)”, the lock word is changed to “value indicating busy (hereinafter, locked)” and the critical section is executed. Also, when the execution of the critical section is finished, the lock word is returned to unlocked.
(2) If the lock word is locked, the process of (1) is executed after waiting until the lock word becomes unlocked.

  By performing the above control, the problem that the process executed by the other processor and the process executed by the own processor compete on the critical section does not occur.

  Some critical sections can be executed by only one thread, and others have an upper limit on the number of executable threads (those that give a lock to a plurality of threads). In addition, a read-write lock that gives two types of locks, write lock (lock related to processing such as writing and updating) and read lock (lock related to processing such as reading and reference) is applied to the critical section. Sometimes. The number of threads that can acquire a write lock and execute a critical section is limited to “1”. On the other hand, there is no upper limit to the number of threads that can acquire a read lock, and a thread that has acquired a read lock can execute a critical section only when there is no thread that has acquired a write lock and is processing.

  Next, general exclusive control when a critical path is executed by a thread will be described in detail.

  If a lock word is locked when a thread enters the critical section and the execution of the critical section cannot be started immediately, the thread waits until the lock word becomes unlocked.

There are two types of methods shown in (1) and (2) below.
(1) A spin loop method in which a thread keeps checking a lock word using a processor resource until the lock word is changed to unlocked.
(2) The thread suspends the use of processor resources and shifts to the sleep state, and wakes up when another thread executing the critical section completes the execution of the critical section. Block system to request (for example, see Patent Document 1).

  Also, a method that combines the spin loop method and the block method (that is, a method that initially waits in accordance with the spin loop method and waits in accordance with the block method after a certain period of time) may be adopted. Many.

  When the block method is adopted, a flag indicating whether or not there is a waiting thread is used in addition to the lock word as a variable for managing the state of the critical section.

  Whichever method is adopted, the thread cannot execute the original process while waiting for the lock acquisition. This becomes a factor that hinders effective use of the capability and performance of the information processing system. In particular, in information processing systems equipped with a large number of processors that have become common with the recent spread of multi-core processors, there is an increasing number of situations where this lock acquisition wait becomes a performance bottleneck. There is a need for a way to do this.

  By the way, two operations, confirmation (reading) of the lock word that is performed when a thread enters the critical section, and change to locked (writing) when the lock word is unlocked require the same treatment as the critical section. It becomes. For this reason, instructions for performing these operations are prepared in a processor having a function for a multiprocessor.

  For example, a cmpxchg instruction is prepared for an Intel x86 processor (see Non-Patent Document 1).

This cmpxchg instruction uses a reserved register (eax register), a register operand, and a memory operand, and the following series (1), (2-1), and (2-2): Is performed atomically.
(1) A value corresponding to the address indicated by the memory operand is read from the memory to the processor.
(2-1) When the read value in the above (1) matches the value of the eax register, the value of the register operand is written in the memory.
(2-2) If the read value in (1) above does not match the value in the eax register, the read value is written into the eax register.

  Note that atomic means that a hardware operation guarantees that no other processor accesses the memory between the memory read operation (1) and the memory write operation (2-1). . An instruction such as the cmpxchg instruction is generally called a CAS (Compare And Swap) instruction. In the present specification, a series of operations by the CAS instruction is referred to as “atomic access”.

  In order to acquire a lock using the above CAS instruction, the CAS instruction is executed by setting unlocked in the eax register, setting locked in the register operand, and setting the address of the lock word in the memory operand. When the lock word is unlocked, the above (2-1) is executed, so that the lock word is rewritten to locked and the value of the eax register does not change.

  On the other hand, when the lock word is locked, the above (2-2) is executed, so that the lock word is not updated and “locked” is set in the eax register. The thread that has executed the CAS instruction can check whether the lock acquisition has succeeded by checking the value of the eax register after the CAS instruction is executed (that is, the critical section is executed, or by another thread). It can be determined whether to wait for the lock word to be changed to unlocked).

  As another related technique, there is a memory management technique for managing a memory by dividing it into a user space and a kernel space (for example, see Non-Patent Document 2).

  Among these, the user space is a memory area in which information (instructions, data, etc.) necessary for the operation of a user program such as an application is arranged, and an independent area is prepared for each process. This user space is usually a target of paging, and when the memory capacity becomes tight, the user space may be saved in the binary storage device. For this reason, information arranged in the user space may not exist on the real memory.

  On the other hand, the kernel space is a memory area in which information necessary for operating a kernel (OS) that performs access to a physical device and system management operates, and is a space common to all processes.

  In the user mode for executing a user program, a process can access data arranged in the user space (hereinafter referred to as user data) but cannot access data arranged in the kernel space (hereinafter referred to as kernel data). . On the other hand, in the kernel mode for executing a program (hereinafter referred to as a kernel program) arranged in the kernel space, the process includes kernel data arranged in the kernel space and user data arranged in the user space belonging to the process. You can access both.

  In addition, when accessing user data from the kernel space, there may be a case where the information to be accessed does not exist in the real memory. Therefore, it is necessary to operate the system correctly even in such a situation. For this reason, information is copied between the user space and the kernel space using a user space read function and a user space write function prepared as kernel functions. When the user data is processed, the kernel copies the user data to the kernel space by the user space read function and writes the result back to the user space by the user space write function.

  In addition, the above lock word is generally arranged in the user space, and the lock acquisition operation is performed in the user program.

Japanese Patent Laid-Open No. 10-161892

Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M, http://www.intell.com/Asset.com/Asset. Maurice J. Bach, THE DESIGN OF THE UNIX OPERATING SYSTEM, PENTICE-HALL, INC. , Englewood Cliffs, New Jersey 07632, 1986

  However, the above-described conventional exclusive control has a problem that the ability and performance of the information processing system cannot be fully utilized. This is because the lock is released after the thread calls the kernel program to request sleep processing due to lock contention and before the kernel program performs sleep processing and transitions the thread to the sleep state. This is because the thread cannot acquire the lock immediately even if it has occurred (the lock acquisition operation cannot be executed unless after returning from the sleep state).

  Therefore, an object of the present invention is to make it possible to more effectively utilize the capability and performance of an information processing system.

  In order to achieve the above object, an exclusive control program according to an aspect of the present invention causes an information processing system that manages a memory separately into a user space and a kernel space to perform exclusive control. The exclusive control program is executed in the kernel space, and the exclusive control is performed when the execution of a critical session in the user program arranged in the user space by one execution unit competes with another execution unit. Atomically accessing the data for managing the contention arranged in the user space, and determining whether the critical section can be executed by the one execution unit.

  An exclusive control method according to an aspect of the present invention provides an exclusive control method in an information processing system that manages a memory separately in a user space and a kernel space. In the exclusive control method, when execution of a critical session in a user program arranged in the user space by one execution unit competes with another execution unit, the exclusive space is arranged from the kernel space to the user space. Atomic access is made to data for managing conflicts, and it is determined whether or not the critical section can be executed by the one execution unit.

  Furthermore, an information processing system according to an aspect of the present invention manages a memory separately in a user space and a kernel space, and executes the exclusive control program in the kernel space.

  In the present invention, a lock acquisition operation is performed from the kernel space. For this reason, if the lock is released between the time when the thread requests sleep processing due to lock contention and the transition to sleep mode, the thread can immediately acquire the lock without sleeping. It becomes. Therefore, the thread can continuously execute the original process, and thus the ability and performance of the information processing system can be utilized more effectively.

It is the block diagram which showed the structural example of the information processing system which concerns on embodiment of this invention. It is the figure which showed the schematic operation example of the exclusive control program which concerns on embodiment of this invention. It is the flowchart figure which showed the operation example of the user space read function, the user space write function, and the user space atomic access function which the exclusive control program which concerns on embodiment of this invention has. It is the flowchart figure which showed the example of whole operation | movement of the information processing system which concerns on embodiment of this invention. It is the figure which showed the structural example of lock word used for the information processing system which concerns on embodiment of this invention. It is the flowchart figure which showed an example of normal lock acquisition operation in the information processing system which concerns on embodiment of this invention. It is the flowchart figure which showed an example of the system call pre-processing in the information processing system which concerns on embodiment of this invention. It is the flowchart figure which showed an example of the lock acquisition operation using the user space atomic access function in the information processing system which concerns on embodiment of this invention. It is the flowchart figure which showed an example of the lock release process in the information processing system which concerns on embodiment of this invention. It is the flowchart figure which showed an example of the process after a sleep in the information processing system which concerns on embodiment of this invention.

  Hereinafter, an exclusive control program according to the present invention and an information processing system that executes the exclusive control program will be described with reference to FIGS. In the drawings, the same components are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.

  An information processing system 1 according to the present embodiment shown in FIG. 1 includes a memory 2 and a plurality of processors (central processing units) 3_1 to 3_n. A user space 10 and a kernel space 20 are formed in the memory 2.

  A user program 11 and user data 12 are arranged in the user space 10. The user data 12 includes a lock word 100 that is data for exclusive control.

  On the other hand, a kernel program 21 and kernel data 22 are arranged in the kernel space 20. The kernel program 21 includes a user space atomic access function 203 in addition to the user space read function 201 and the user space write function 202 described above. Here, the user space atomic access function 203 atomically accesses the lock word 100 as will be described later. The kernel program 21 executes a lock acquisition operation from the kernel space 20 by using the user space atomic access function 203.

  Each processor 3_1 to 3_n generates one or more threads (not shown). Each thread reads a machine language instruction to be executed from the user program 11 or the kernel program 21, and executes a process defined by the machine language instruction. At this time, each thread uses the user data 12 or the kernel data 22 as necessary.

  The access from the user program 11 to the user data 12 and the access from the kernel program 21 to the kernel data 22 are not limited as in a general information processing system. That is, each of the processors 3_1 to 3_n can perform reading, writing, and atomic access by executing a machine language instruction without using a special function.

  The user program 11 and the kernel program 21 generally operate as shown in FIG.

  As shown in FIG. 2, when using the function of the kernel program 21, the user program 11 makes a system call to shift to the kernel mode, and causes the kernel program 21 to execute processing. When the process by the kernel program 21 is completed, the kernel program 21 returns to the user program 11 and returns to the user mode, and thus the process by the user program 11 is continued. When using the user data 12, the kernel program 21 uses the user space read function 201, the user space write function 202, or the user space atomic access function 203 depending on the type of access.

  These functions 201 to 203 generally operate as shown in FIG.

  As shown in FIG. 3, each of the functions 201 to 203 first checks whether an access target area exists in the memory 2 (step S1). As a result, when it is determined that the access target area exists in the memory 2, each of the functions 201 to 203 executes an access process predetermined for the function (step S2). That is, the user space read function 201 performs read access to the user data 12, the user space write function 202 performs write access to the user data 12, and the user space atomic access function 203 performs the lock access to the lock word 100. Perform atomic access.

  On the other hand, if it is determined in step S1 that the access target area does not exist in the memory 2, each function 201 to 203 executes a page fault process and is saved in a secondary storage device (not shown). The memory area being returned is returned to the real memory (step S3). When the page fault process is successful (step S4), each of the functions 201 to 203 proceeds to the above step S2 and executes a predetermined access process. If the page fault process is not successful, the functions 201 to 203 end abnormally assuming that the access process to the user space has failed.

  Next, a specific operation example of the present embodiment will be described in detail with reference to FIGS.

  Prior to the execution of the critical section in the user program 11, the thread operating in the information processing system 1 executes the lock acquisition process shown in FIG. Specifically, the thread first initializes the number of retries 300 to “0” in preparation for a lock acquisition failure (step S11).

  Then, the thread executes a normal lock acquisition operation in the user mode (step S12). Specifically, for example, the thread executes the process shown in FIG. 6 on the lock word 100 configured as shown in FIG. Here, the lock word 100 includes a 1-bit lock bit 101 and a 10-bit blocked thread number 102. The lock word 100 has a data length that can be handled by a CAS instruction. Further, lock bit 101 = “0” means unlocked, and lock bit 101 = “1” means locked. Further, the number of threads that enter the sleep state due to lock contention is counted as the number of blocked threads 102.

  As shown in FIG. 6, the thread first assigns the lock word 100 to the work variable old having the same data length and data structure as the lock word 100 (step S31). Then, the thread determines whether or not the lock bit of the variable old is “0” (step S32).

  As a result, when lock bit = “0” is satisfied, the thread copies the variable old to the work variable new having the same data length and data structure as the lock word 100 (step S33), and then lock bit of the variable new. Is set to "1" (step S34).

  Then, the thread sets the variable old in the eax register, the variable new in the register operand, and the address of the lock word 100 in the memory operand, and executes the CAS instruction (step S35). When the CAS instruction is successful (step S36), since “1 (locked)” is set in the lock bit 101 of the lock word 100, the thread finishes the process on the assumption that the lock has been successfully acquired. If the CAS instruction has failed (that is, if lock word 100 has been changed by another thread while executing steps S32 to S34 above), the thread returns to step S32 above to acquire the lock operation. Run again. At this time, the latest lock word 100 is substituted for the variable old.

  On the other hand, when lock bit = “1” is established in the above step S32, the thread finishes the process on the assumption that the lock acquisition has failed.

  Returning to FIG. 4, when the above-described normal lock acquisition operation is successful (step S13), the thread ends the lock acquisition process and executes the critical section.

  On the other hand, when the normal lock acquisition operation fails, the thread repeatedly executes the normal lock acquisition operation while incrementing the number of retries 300 until reaching a predetermined threshold (steps S14 and S15). . When the number of retries 300 reaches the threshold value, the thread determines that it is necessary to activate a system call for shifting to the sleep state (hereinafter referred to as a sleep system call).

  Then, prior to the activation of the sleep system call, the thread executes the preprocessing shown in FIG. 7 (step S16), and thereby increments the number of blocked threads 102 of the lock word 100. Specifically, the thread first assigns the lock word 100 to the variable old (step S41). Then, after copying the variable old to the variable new (step S42), the thread increments the number of blocked threads of the variable new by “1” (step S43). Then, the thread executes the CAS instruction in the same manner as in the above step S35 (step S44). When the CAS instruction is successful (step S45), the number of blocked threads 102 of the lock word 100 is incremented by “1”, so that the thread activates a sleep system call (step S17 in FIG. 4). On the other hand, if the CAS instruction has failed, the thread returns to step S42 to retry incrementing the blocked thread number 102.

  Returning to FIG. 4, when the sleep system call is activated, the thread transitions to the kernel mode and executes a lock acquisition operation using the user space atomic access function 203 (step S <b> 18).

  Specifically, as shown in FIG. 8, the thread first assigns lock word 100 to the variable old (step S51). Then, the thread determines whether or not the lock bit of the variable old is “0” (step S52).

  As a result, if lock bit = “0” is satisfied, the thread copies the variable old to the variable new (step S53), sets the lock bit of the variable new to “1” (step S54), and sets the variable new. The number of blocked threads of “1” is decremented by “1” (step S55). Then, the thread executes the CAS instruction in the same manner as in the above step S35 (step S56). If the CAS instruction is successful (step S57), the thread ends the process assuming that the lock has been successfully acquired. If the CAS instruction fails, the thread returns to step S52 to execute the lock acquisition operation again.

  On the other hand, when lock bit = “1” is established in step S52 described above, the thread terminates the process on the assumption that the lock acquisition has failed.

  Returning to FIG. 4, when the lock acquisition operation using the user space atomic access function 203 is successful (step S19), the thread immediately ends the system call and returns to the user mode (step S20). The lock acquisition process ends.

  As a result, the thread can immediately acquire the lock without executing sleep and execute the critical section. For this reason, the capability and performance which the information processing system 1 has can be utilized effectively.

  On the other hand, when the lock acquisition operation using the user space atomic access function 203 fails, the thread executes a sleep process (interrupts the use of processor resources) and shifts to a sleep state (step S21).

  This sleep state is released when another thread that has acquired the lock finishes executing the critical section and executes a process for releasing the lock (hereinafter referred to as a lock release process).

  Specifically, as shown in FIG. 9, the other threads first assign the lock word 100 to the variable old (step S61). Then, the other thread copies the variable old to the variable new (step S62), and then sets the lock bit of the variable new to “0” (step S63). Then, the other threads execute the CAS instruction in the same manner as in the above step S35 (step S64).

  When the CAS instruction is successful (step S65), the other threads determine whether or not the number of blocked threads of the variable old is “0”. When the number of blocked threads = “0” is satisfied (step S66), the other threads end the lock release process. On the other hand, when the number of blocked threads = “0” is not satisfied, the other threads execute the wake-up process for the thread in the sleep state, and then terminate the lock release process (step S67).

  On the other hand, if the CAS instruction fails, the other thread returns to step S62 and executes the lock release process again.

  Returning to FIG. 4, when the sleep state is released by the above-described lock release processing, the thread executes post-processing shown in FIG. 10 (step S <b> 22), and thus decrements the number of blocked threads 102 of the lock word 100. Specifically, the thread first assigns the lock word 100 to the variable old (step S71). Then, after copying the variable old to the variable new (step S72), the thread decrements the number of blocked threads of the variable new by “1” (step S73). Then, the thread executes the CAS instruction in the same manner as in the above step S35 (step S44). If the CAS instruction is successful (step S75), the number of blocked threads 102 of the lock word 100 is decremented by “1”, and the thread ends post-processing. On the other hand, if the CAS instruction has failed, the thread returns to step S72 to retry decrementing the number of blocked threads 102.

  Thereafter, the thread ends the sleep system call and returns to the user mode (step S23 in FIG. 4). At this time, unlike the step S20, the thread returns to the step S11 and executes the lock acquisition process again. Note that the thread may return to the above-described step S18 without returning to the user mode after the sleep state is cancelled, and thus execute the lock acquisition operation using the user space atomic access function 203 again.

  Note that the present invention is not limited to the above-described embodiments, and it is apparent that various modifications can be made by those skilled in the art based on the description of the scope of the claims.

  The present invention is applied to an exclusive control program, an exclusive control method, and an information processing system, and is particularly applied to an application for performing exclusive control when a critical path is executed by a plurality of threads.

DESCRIPTION OF SYMBOLS 1 Information processing system 2 Memory 3_1-3_n Processor 10 User space 11 User program 12 User data 20 Kernel space 21 Kernel program 22 Kernel data 100 Lock word (exclusive control data)
101 lock bit
102 Number of blocked threads 201 User space read function 202 User space write function 203 User space atomic access function 300 Retry count

Claims (7)

An exclusive control program for performing exclusive control in an information processing system that manages memory separately in user space and kernel space,
The exclusive control program is executed in the kernel space,
The exclusive control is for managing the contention arranged in the user space when the execution of a critical session in the user program arranged in the user space by one execution unit competes with another execution unit. An exclusive control program comprising: accessing data atomically and determining whether or not the critical section can be executed by the one execution unit. In claim 1,
The exclusive control program includes detecting the occurrence of the contention when the one execution unit requests a transition to its sleep state. In claim 1 or 2,
The exclusive control determines that the critical section can be executed by the one execution unit when the data indicates resolution of the conflict, and gives the execution right of the critical section to the one processing unit. Includes exclusive control program. An exclusive control method in an information processing system for managing memory by dividing it into user space and kernel space,
When the execution of a critical session in a user program arranged in the user space by one execution unit competes with another execution unit, for managing the competition arranged in the user space from the kernel space An exclusive control method for accessing data atomically and determining whether the critical section can be executed by the one execution unit. In claim 4,
An exclusive control program for detecting the occurrence of the contention when the one execution unit requests a transition to its sleep state. In claim 4 or 5,
An exclusive control method for determining that execution of the critical section by the one execution unit is possible when the data indicates resolution of the conflict, and giving the execution right of the critical section to the one processing unit. An information processing system that manages memory separately in user space and kernel space,
An information processing system that executes the exclusive control program according to claim 1 in the kernel space.

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