JP3149864B2 - Processing frequency guarantee circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing count guarantee circuit for guaranteeing a predetermined (or externally designated) number of continuous processes when a trigger (instruction) is input from the outside. .

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 10-1 discloses a method for continuously performing a predetermined (or externally specified) number of times when a trigger (instruction) is input from the outside.
There is an "information processing circuit, microcomputer, and electronic device" disclosed in JP-A-34032. In this method, the number of executions is set in a register at the beginning of the process,
Each time the process is performed once, the number of executions stored in the register is decremented (-1), and the process is terminated when the value of the register becomes "0".

[0003]

However, according to this, when a trigger (instruction) is input from the outside under the condition that "a predetermined number of processes must be performed within a certain period" In this case, processing cannot be temporarily and continuously performed for a predetermined number of times (or specified from the outside).

The reason is that, in the prior art, a certain number of processes can be continuously performed by inputting a trigger (product-sum operation command) from the outside, but the normal operation (normal operation) is performed. Although the processing timing is not mentioned, the control is not performed so as to perform a predetermined number of times of processing separately at least within a predetermined period.

As a circuit for realizing the above-mentioned processing under the above-mentioned conditions by applying the conventional technique, for example, the following form shown in FIG. 4 can be considered.

[0006] The number of continuous processing is set when a continuous processing request is input, and the counter 10 decrements the value when the output of the AND circuit 11 is at the H level. If the value of the counter 10 is larger than "0", the counter 10 becomes H A comparison circuit 12 that outputs a level and outputs an L level when the value of the counter 10 is “0”; an AND circuit 11 that outputs a logical product of the output result of the comparison circuit 12 and the shortest processing cycle signal; A processing circuit 30 that is required to perform processing a predetermined number of times within a predetermined period, and performs processing only when the output result of the OR circuit 31 is at the H level; An AND circuit 32 for outputting a logical product of the shortest processing cycle signal and an OR circuit 31 for outputting a logical sum of an output result of the AND circuit 32 and a processing control signal.

[0007]

SUMMARY OF THE INVENTION The present invention has been developed in such a manner that a processing circuit which is required to perform processing a certain number of times within a certain period is irregularly or periodically. If a continuous processing request is entered,
By performing processing continuously for a specified number of times and masking a processing control signal that is input thereafter for the number of times of continuous processing, a predetermined (or externally specified) ) Temporary continuous processing for the number of times can be surely guaranteed.

That is, in the basic configuration of the processing count assurance circuit according to the present invention, the given continuous processing count is decremented by the first counter each time an external shortest processing cycle signal is input, and the value is set to "0". A continuous processing means for continuously inputting an enable signal to the processing circuit until the value of the first counter becomes "0"; And a continuous processing prohibiting means for prohibiting the input of the enable signal to the processing circuit until the value becomes "0".

As shown in FIG. 1, a first embodiment of the present invention which embodies such a basic configuration includes a first counter 10 and a number of continuous processes simultaneously input when a continuous process request is input.
And the operation result of the first operation circuit 13 is set when a continuous processing request is input, and the value is decremented when the output of the first AND circuit 11 is at one level. The first counter 10 and the first counter 1
The first comparison circuit 12 outputs different levels when the value of 0 is greater than “0” and when the value of the first counter 10 is “0”, and the output result of the first comparison circuit 12 First AND circuit 11 for outputting a logical product with the shortest processing cycle signal
And a second arithmetic circuit 23 for adding the number of continuous processes simultaneously input at the time of input of the continuous processing request and the value of the second counter 20, and setting the operation result of the second arithmetic circuit 23 at the time of the continuous processing request input The second counter 2 decrements the value when the output of the second AND circuit 21 is at one level.
0, a second comparison circuit 22 that outputs different levels when the value of the second counter 20 is greater than “0” and when the value of the second counter 20 is “0”; A second AND circuit 21 that outputs the logical product of the output result of the comparison circuit 22 and the processing control signal, and a request to perform processing a predetermined number of times separately within a predetermined period, and a logical sum A processing circuit 30 that performs processing only when the output result of the circuit 31 is at one level, a third AND circuit 32 that outputs a logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal, A logical inverting circuit 34 for logically inverting the output result of the second comparing circuit 22, a fourth logical AND circuit 33 for outputting a logical AND of the logical inverting circuit 34 and the processing control signal, and a third logical AND circuit 32 And the output result of the fourth AND circuit 33 A first OR circuit 13 for adding the value of the first counter 10 to the number of continuous processes input simultaneously when a continuous process request is input, comprising: The operation result of the operation circuit 13 is set when a continuous processing request is input, and the value of the first counter 10 that decrements the value when the output of the first AND circuit 11 is at one level, and the value of the first counter 10 is “
When it is larger than 0, the value of the first counter 10 becomes "0"
1st comparison circuit 12 which outputs a different level between
A first AND circuit 11 for outputting a logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal; A second arithmetic circuit 23 that adds the value of
A second counter 20 that sets the operation result of the second operation circuit 23 when a continuous processing request is input, and decrements the value when the output of the second AND circuit 21 is at one level; A second comparison circuit 22 that outputs different levels when the value is greater than “0” and when the value of the second counter 20 is “0”, and the output result of the second comparison circuit 22 and the processing control A second AND circuit 21 which outputs a logical product of the signal and a second logical AND circuit 31 which is required to perform processing a predetermined number of times separately within a predetermined period;
And a third and third AND circuit 32 for outputting a logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal.
A logical inversion circuit 34 for logically inverting the output result of the second comparison circuit 22, a fourth AND circuit 33 for outputting a logical product of the logical inversion circuit 34 and the processing control signal, and a third logical product An OR circuit 3 that performs an OR operation on the output result of the circuit 32 and the output result of the fourth AND circuit 33 and outputs the result to the processing circuit 30
And 1.

In the second embodiment of the present invention, as shown in FIG. 2, the number of continuous processes is set when a continuous process request is input.
When the output of the first AND circuit 11 is at one level, the first counter 10 decrements the value, when the value of the first counter 10 is greater than "0",
A first comparison circuit 12 that outputs a different level when the value of 0 is “0”, and a first AND circuit that outputs a logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal Circuit 1
1 and the number of continuous processes are set when a continuous process request is input, and when the output of the second AND circuit 21 is at one level, the value of the second counter 20 is decremented. When the value is greater than 0 "and the second counter 20
The second comparison circuit 22 outputs a different level when the value of “0” is “0”, and the second AND circuit 21 outputs the AND of the output result of the second comparison circuit 22 and the processing control signal When,
A processing circuit 30 that is required to perform processing a predetermined number of times within a predetermined period, and performs processing only when the output result of the OR circuit 31 is at one level; A third AND circuit 32 that outputs a logical product of the output result of the shortest processing cycle signal and a logical inverting circuit 34 that logically inverts the output result of the second comparing circuit 22;
A fourth AND circuit 33 that outputs the logical product of the logical inversion circuit 34 and the processing control signal, and the output result of the third logical product circuit 32 and the output result of the fourth logical product circuit 33 are ORed. And an OR circuit 31 which outputs the result to the processing circuit 30.

Further, according to a third embodiment of the present invention, as shown in FIG. 3, the number of times of continuous processing input simultaneously with the input of a continuous processing request and the value of the first counter 10 are added and the first is subtracted. The operation result of the first operation circuit 13 and the operation result of the first operation circuit 13 are set when a continuous processing request is input, and the first AND circuit 11
When the value of the first counter 10 is greater than "0", and when the value of the first counter 10 is "0". A first comparison circuit for outputting different levels, a first AND circuit for outputting a logical product of an output result of the first comparison circuit and a shortest processing cycle signal, and a simultaneous input when a continuous processing request is input A second arithmetic circuit 23 for adding and subtracting 1 from the number of consecutive processes to be performed and the value of the second counter 20;
A second counter 20 that sets the operation result of the second operation circuit 23 when a continuous processing request is input, and decrements the value when the output of the second AND circuit 21 is at one level; A second comparison circuit 22 that outputs different levels when the value is greater than “0” and when the value of the second counter 20 is “0”, and the output result of the second comparison circuit 22 and the processing control A second AND circuit 21 which outputs a logical product of the signal and a second logical AND circuit 31 which is required to perform processing a predetermined number of times separately within a predetermined period;
A processing circuit 30 that performs processing only when the output result of the first comparison circuit is at one level, a third AND circuit 32 that outputs the logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal, A logical inversion circuit 34 for logically inverting the output result of the comparison circuit 22, a fourth AND circuit 33 for outputting a logical product of the logical inversion circuit 34 and the processing control signal, and an output of the third logical product circuit 32 An OR circuit 31 that performs an OR operation on the result and the output result of the fourth AND circuit 33 and outputs the result to the processing circuit 30;
Consists of

In the above first, second and third embodiments,
It is not always the case that both the first and second arithmetic circuits 13 and 14 are necessary, and only one of them may be sufficient. For example, when a continuous processing request is input, the first counter 10 is always “0” and the second counter 20
If is not necessarily “0”, the first arithmetic circuit 13 is unnecessary, and the necessity of the first and second arithmetic circuits 13 and 14 is individually determined depending on the use conditions.

[0013]

FIG. 1 shows a configuration in the case where the shortest processing cycle is equal to or longer than two clock times and the load timing input to the first counter 10 and the second counter 20 is earlier than the enable timing. The timing and the enable timing are included in one processing time.)
If the continuous processing request is input again before the value of the first counter 10 becomes “0”, the value set in the first counter 10 at the time of inputting the continuous processing request is “the first counter at the time of inputting the continuous processing request”. 10 + the number of continuous processing this time. " When the continuous processing request is input again before the value of the second counter 20 becomes “0”, the value set in the second counter 20 at the time of inputting the continuous processing request is set to “the second counter at the time of inputting the continuous processing request”. 20 + current number of continuous processing ”.

In the case of the second embodiment shown in FIG. 2, it is assumed that the next continuous processing request is not input until the value of the first counter 10 becomes "0". The set value of the counter 10 is defined as the number of continuous processes. Because, when a continuous processing request is input, the value of the first counter 10 is always “0”, and the result of the first arithmetic circuit 12 in FIG. 1 is equal to “the number of continuous processing”. This arithmetic circuit 12 becomes unnecessary.

In the case of the second embodiment shown in FIG. 2, it is assumed that the next continuous processing request is not input until the value of the first counter 20 becomes "0". The set value of the counter 20 is defined as the number of continuous processes. This is because the value of the second counter 20 is always “0” when a continuous processing request is input, and the result of the second arithmetic circuit 22 in FIG. The arithmetic circuit 22 becomes unnecessary. The timing at which the counter value becomes “0” is determined by the first and second counters 1.
Different at 0,20. The second counter 20 is slower.

In the case of the third embodiment shown in FIG. 3, it is assumed that the load timing input to the first counter 10 and the enable timing overlap each other, and the value set in the first counter 10 is set to "continuous processing request input". The value of the first counter 10 at the time + the current number of continuous processing times−1 ”. However, the first counter 10 is a counter that gives priority to loading when the input load timing and the enable timing overlap. In this case, even the shortest processing cycle is one clock.

In the case of the third embodiment shown in FIG. 3, it is assumed that the load timing and the enable timing input to the second counter 20 overlap, and the value set in the second counter 20 is set to "continuous processing". The value of the second counter 20 at the time of inputting the request + the current number of continuous processing times−1 ”.
However, if the input load timing and the enable timing overlap, the second counter 20 is a counter that gives priority to loading. In this case, even the shortest processing cycle is one clock.

[0018]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. The processing number assurance circuit includes a first arithmetic circuit 13 for adding the number of continuous processings simultaneously input at the time of inputting a continuous processing request and a value of the first counter 10, and a processing result of the first arithmetic circuit 13. The first counter 10 is set when a processing request is input and decrements when the output of the first AND circuit 11 is at the H level, and the value of the first counter 10 is “0”.
When the value of the first counter 10 is "0", the first comparison circuit 12 outputs an H level when the value of the first counter 10 is "0". First AND circuit 11 for outputting a logical product with a periodic signal
And a second arithmetic circuit 23 for adding the number of continuous processes simultaneously input at the time of input of the continuous processing request and the value of the second counter 20, and setting the operation result of the second arithmetic circuit 23 at the time of the continuous processing request input And a second counter 20 that decrements the value when the output of the second AND circuit 21 is at the H level.
When the value of the second counter 20 is larger than "0", the H level is output, and the value of the second counter 20 is set to "0".
A second comparison circuit 22 that outputs an L level; a second AND circuit 21 that outputs a logical product of the output result of the second comparison circuit 22 and the processing control signal; A processing circuit 30 that is required to perform processing a predetermined number of times determined separately during the period, and performs processing only when the output result of the OR circuit 31 is at the H level, and the output result of the first comparison circuit 12 and the shortest processing A third AND circuit 32 that outputs a logical product of the periodic signal, a logical inverting circuit 34 that logically inverts the output result of the second comparing circuit 22, and a logical product of the logical inverting circuit 34 and the processing control signal. Output fourth AND circuit 33
And an OR circuit 31 that performs an OR operation on the output result of the third AND circuit 32 and the output result of the fourth AND circuit 33 and outputs the result to the processing circuit 30.

The operation of the first embodiment will be described with reference to FIG. A signal that causes the processing circuit 30 to operate a certain number of times in a certain period in a pre-stage circuit (not shown) is generated and input to the circuit in the figure as a processing control signal. As this processing control signal, for example, a periodic pulse signal can be considered. When the control by the first counter 10 and the second counter 20 is not performed by the continuous processing request input, the processing circuit 30 executes the processing in accordance with the processing control signal.

In order to maintain the processing cycle of the processing circuit 30, the input timing of the processing control signal is obtained by thinning out the input pulse (H level) of the shortest processing cycle signal. For example, as shown in FIG. 5, when the processing time of the processing circuit 30 is 3 clocks, the shortest processing cycle signal is 3 clocks.
A signal which becomes H level in the clock cycle, the interval between the H levels of the processing control signal is an integral multiple of three clocks, and the timing when the H level becomes the H level of the shortest processing cycle always coincides. And

When a continuous processing request is input, the output result of the first arithmetic circuit 13 is loaded into the first counter 10. When the output of the first comparison circuit 12 is at the H level, the gate of the first AND circuit 11 is opened, and the shortest processing cycle is set to enable the countdown of the first counter 10 (E
N). When the enable is input, the first counter 10 decrements the value. The first comparison circuit 12 outputs an H level when the value of the first counter 10 is larger than “0”, and outputs an L level when the value of the first counter 10 is “0”.

When a continuous processing request is input, the output result of the second arithmetic circuit 23 is loaded into the second counter 20. When the output of the second comparison circuit 22 is at the H level, the gate of the second AND circuit 21 is opened, and the processing control signal is used to enable the countdown of the second counter 20 (E
N). When the enable is input, the second counter 20 decrements the value. The second comparison circuit 22 outputs the H level when the value of the second counter 20 is larger than “0”, and outputs the H level when the value is “0”.
Output level.

When the output of the first comparison circuit 12 is at the H level, the gate of the third AND circuit 32 is opened, and the shortest processing cycle is input to the OR circuit 31. Therefore, regardless of the interval at which the processing control signal is input,
The enable signal is continuously input to the processing circuit 30 for the number of continuous processing.

The output of the second comparison circuit 22 is controlled so that the subsequent normal processing is stopped in order to recover the amount of the continuous processing performed by the first counter 10. When the output of the second comparison circuit 22 is at the H level, it is inverted to the L level by the logic inversion circuit 34, so that the gate of the fourth AND circuit 33 is closed so that the processing control signal is not output. Become. Therefore, the enable is not input to the processing circuit 30 while the processing control signal is input for the number of times of the continuous processing.

FIG. 6 is a time chart showing the timing of these operations. FIG. 6 shows, in chronological order, when the processing control signal is not input while the continuous processing is being performed, or when the processing control signal is input while the continuous processing is being performed, the first counter 10 and the second This shows a case where a continuous processing request is input again before the second counter 20 becomes “0”. The number of processings when there is no continuous processing request is the number of H levels of the processing control signal, and the number of processings when the operation for performing the continuous processing and guaranteeing the processing performed collectively is performed by the OR circuit 31. This is the number of output H levels. Since each number is equal,
It can be seen that the number of times of processing as a whole is guaranteed.

Next, a second embodiment of the present invention is shown in FIG. The processing count assurance circuit sets the continuous processing count when a continuous processing request is input, and sets the output of the first AND circuit 11 to H
First counter 10 that decrements the value at the level
When the value of the first counter 10 is greater than "0", the H level is output, and the value of the first counter 10 is "0".
In the case of, the first comparison circuit 12 that outputs the L level, the first AND circuit 11 that outputs the logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal, The second counter 20 is set when a continuous processing request is input and decrements when the output of the second AND circuit 21 is at the H level. When the value of the second counter 20 is greater than “0”, the second counter 20 is set to H. The second comparison circuit 22 outputs a low level when the value of the second counter 20 is "0".
And a second AND circuit 21 that outputs the logical product of the output result of the second comparison circuit 22 and the processing control signal, and that the processing is performed a predetermined number of times within a predetermined period. A processing circuit 30 that performs processing only when the output result of the OR circuit 31 is H level, and a first comparison circuit 1
A third AND circuit 32 that outputs a logical product of the output result of the second and the shortest processing cycle signal, a logical inverting circuit 34 that logically inverts the output result of the second comparing circuit 22, and a logical inverting circuit 34. A fourth AND circuit 33 that outputs a logical product of the processing control signal, and an output result of the third logical product circuit 32 and an output result of the fourth logical product circuit 33 to perform a logical OR operation on the processing circuit 3
And an OR circuit 31 for outputting to 0.

Since the basic operation of the second embodiment is the same as that of the first embodiment, only different points will be described.

Since the first arithmetic circuit 13 shown in the first embodiment adds the value of the first counter 10 to the number of continuous processings, the value of the first counter 10 becomes "".
If a continuous processing request is input only when the value is "0", the first arithmetic circuit 13 becomes unnecessary, and the number of continuous processing can be used as it is as the load value of the first counter 10. In addition, the second arithmetic circuit 23
Since the value of the second counter 20 is added to the number of continuous processes, it is clear that the value of the second counter 20 is always "0" when a continuous process request is input. For example, the second arithmetic circuit 23 becomes unnecessary, and the number of continuous processes can be used as the load value of the second counter 20 as it is. FIG. 2 illustrates a case where neither the first operation circuit 13 nor the second operation circuit 23 is required, but it is also possible to delete only one of them.

The operation is performed only by the difference between whether the load value to the first counter 10 or the second counter 20 uses the output of the arithmetic circuit or the number of continuous processing as it is.
The timing is the same as in the first embodiment.

FIG. 3 shows a third embodiment of the present invention. The processing number assurance circuit includes a first arithmetic circuit 13 for adding the number of continuous processings and a value of the first counter 10 which are simultaneously input when a continuous processing request is input and subtracting 1 from the first processing circuit. A result is set when a continuous processing request is input, and when the output of the first AND circuit 11 is at H level, the value is decremented when the first counter 10 is greater than "0". Outputs the H level, and outputs the L level when the value of the first counter 10 is "0". The output of the first comparison circuit 12 and the shortest processing cycle signal A first AND circuit 11 that outputs a logical product, a second arithmetic circuit 23 that adds the value of the second counter 20 and subtracts 1 from the number of continuous processes simultaneously input when a continuous process request is input, The operation result of the second operation circuit 23 needs to be continuously processed. Set on input, a second AND circuit 2
The second counter 20 decrements the value when the output of 1 is at the H level, and outputs the H level when the value of the second counter 20 is greater than "0".
Is "0", a second comparison circuit 22 that outputs an L level, a second AND circuit 21 that outputs a logical product of the output result of the second comparison circuit 22 and the processing control signal, A processing circuit 30 that is required to perform processing a predetermined number of times within a predetermined period, and performs processing only when the output result of the OR circuit 31 is at the H level; A third AND circuit 32 that outputs a logical product of the output result of the second processing circuit and the shortest processing cycle signal, a logical inverting circuit 34 that logically inverts the output result of the second comparing circuit 22, A fourth AND circuit 33 that outputs a logical product of the signals, a processing result of the logical sum of an output result of the third logical product circuit 32 and an output result of the fourth logical product circuit 33,
And an OR circuit 31 for outputting to 0.

The basic operation of the third embodiment is the same as that of the first embodiment, and only different points will be described.

In the first embodiment, as shown in FIG. 6, both the first counter 10 and the second counter 20 are configured to have different enable and load timings. In the embodiment, the configuration in the case where the enable and the load timing match is shown.

In a general counter, when enable and load are instructed at the same time, the load is given priority. So the load value is entered correctly,
Since the enable which has been input at the same time is ignored, the result is shifted with respect to the number of processes to be adjusted. In order to avoid this, the operation of the first arithmetic circuit 13 is defined as "the value of the counter 10 + the number of continuous processing times-1". In anticipation of one ignored enable process, the value to be loaded is decremented by one so that the number of processes is correct.

Note that this circuit does not operate properly with a counter that gives priority to enable when enable and load match.

Although the processing circuit 30 is shown in FIGS. 1 to 4, the gist of the present invention is that the processing circuit 30 is defined as “a processing scheduled to be executed a certain number of times within a certain period. While the basic operation is to execute the process according to the control signal, when the continuous process request is input, it is possible to execute the process continuously for a specified number of times, and even when the continuous process is performed, a predetermined process is performed. It is an object to provide a mechanism (circuit) for performing control such that “the process is executed a predetermined number of times determined separately within a predetermined period”. Therefore, the processing circuit 30 is not an essential component of the present invention.

[0037]

According to the present invention, a processing circuit which is controlled so as to perform a predetermined number of times of processing separately within a predetermined period of time ("processing control" in the figure) is used for the processing circuit. Even if it is necessary to perform the processing continuously by an external instruction (“continuous processing trigger” in the figure) separately from the control,
It is possible to guarantee a predetermined number of times of processing performed separately within a predetermined period.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment.

FIG. 3 is a block diagram of a third embodiment.

FIG. 4 is a block diagram of a circuit configuration on which the present invention is based.

FIG. 5 is a timing chart showing the timing of a processing control signal for operating the processing circuit in FIG. 1;

FIG. 6 is a timing chart illustrating an operation example of each circuit illustrated in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st counter 11 1st AND circuit 12 1st comparison circuit 13 1st arithmetic circuit 20 2nd counter 21 2nd AND circuit 22 2nd comparison circuit 23 2nd arithmetic circuit 30 Processing Circuit 31 OR circuit 32 Third AND circuit 33 Fourth AND circuit 34 Logical inversion circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/46

Claims (4)

(57) [Claims] 1. A processing number guarantee circuit for a processing circuit required to perform processing a predetermined number of times within a predetermined time period, wherein a given number of continuous processing times is determined by an external device. A continuous processing means for decrementing each time the shortest processing cycle signal is input by the first counter and continuously inputting an enable signal to the processing circuit until the value becomes "0"; and a value of the first counter. Becomes "0", the number of continuous processings is decremented by the second counter each time the shortest processing cycle signal is input, and the value becomes "0".
And a continuous processing prohibiting means for prohibiting input of an enable signal to the processing circuit until the processing signal becomes 0 ". 2. A first arithmetic circuit 13 for adding the number of continuous processes simultaneously input when a continuous process request is input and a value of a first counter 10; A first counter 10 which is set at the time of input and decrements when the output of the first AND circuit 11 is at one level, when the value of the first counter 10 is larger than "0", A first comparison circuit for outputting a different level when the value of the counter is "0"; a first logic for outputting a logical product of an output result of the first comparison circuit and a shortest processing cycle signal A product circuit 11 and a second arithmetic circuit 2 that adds the value of the second counter 20 to the number of continuous processes input simultaneously when a continuous process request is input
3, a second counter 20 for setting the operation result of the second operation circuit 23 when a continuous processing request is input, and decrementing the value when the output of the second AND circuit 21 is at one level; A second comparison circuit 22 that outputs different levels when the value of the counter 20 is greater than “0” and when the value of the second counter 20 is “0”; and an output result of the second comparison circuit 22 A second AND circuit 21 that outputs a logical product of the AND control signal and a processing control signal; and a request is made to perform processing a predetermined number of times separately within a predetermined period, and the output result of the logical sum circuit 31 is A processing circuit 30 that performs processing only at one level; a third AND circuit 32 that outputs the logical product of the output result of the first comparing circuit 12 and the shortest processing cycle signal; and a second comparing circuit 22 Logical inversion circuit 34 for logically inverting the output result of , A fourth AND circuit 33 for outputting a logical product of the processing control signal and the logic inversion circuit 34, the output result and a fourth AND circuit 3 of the third AND circuit 32
And a logical sum circuit 31 for performing a logical sum of the output result of No. 3 and output to the processing circuit 30. 3. A first counter 10 for setting the number of continuous processing when a continuous processing request is input, and decrementing the value when the output of the first AND circuit 11 is at one level; Is greater than “0”, and the first counter 10 outputs different levels when the value of the first counter 10 is “0”. The output result of the first comparator 12 and the shortest processing cycle A first AND circuit 11 for outputting a logical AND with a signal; and a second circuit for setting the number of continuous processes when a continuous processing request is input and decrementing the value when the output of the second AND circuit 21 is at one level. A second comparison circuit 22 that outputs different levels when the value of the second counter 20 is greater than “0” and when the value of the second counter 20 is “0”; The output result of the second comparison circuit 22 and the processing control signal A second AND circuit 21 that outputs a logical product; and a process that is required to perform processing a predetermined number of times separately within a predetermined period, and only when the output result of the OR circuit 31 is at one level. A processing circuit 30 that performs processing; a third AND circuit 32 that outputs the logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal; and a logical inversion of the output result of the second comparison circuit 22 A fourth AND circuit 33 that outputs a logical product of the logical inverting circuit 34 and the processing control signal; an output result of the third logical AND circuit 32 and the fourth logical AND circuit 3
And a logical sum circuit 31 for performing a logical sum of the output result of No. 3 and output to the processing circuit 30. 4. A first arithmetic circuit 13 for adding the number of continuous processes simultaneously input at the time of inputting a continuous process request and the value of the first counter 10 and subtracting 1 from the first arithmetic circuit 13. A first counter 10 that is set when a continuous processing request is input and decrements the value when the output of the first AND circuit 11 is at one level; when the value of the first counter 10 is greater than “0”; A first comparison circuit 12 that outputs a different level when the value of the first counter 10 is "0"; and a second circuit that outputs a logical product of the output result of the first comparison circuit 12 and the shortest processing cycle signal. One logical product circuit 11, a second arithmetic circuit 23 for adding the number of continuous processes simultaneously input at the time of input of the continuous process request and the value of the second counter 20 and subtracting 1 from the other, and a second arithmetic circuit 23 Set the operation result at the time of continuous processing request input, When the output of the second AND circuit 21 is at one level, the second counter 20 decrements the value. When the value of the second counter 20 is larger than "0", and when the value of the second counter 20 is " A second comparison circuit 22 that outputs a different level at the time of “0”; a second AND circuit 21 that outputs a logical product of the output result of the second comparison circuit 22 and the processing control signal; A processing circuit 30 that is required to perform processing a predetermined number of times within a predetermined period, and performs processing only when the output result of the OR circuit 31 is at one level, and an output of the first comparison circuit 12 A third AND circuit 32 that outputs a logical product of the result and the shortest processing cycle signal, a logical inverting circuit 34 that logically inverts the output result of the second comparing circuit 22, a logical inverting circuit 34, a processing control signal, The fourth logical product that outputs the logical product of A circuit 33, an output result of the third AND circuit 32, and a fourth AND circuit 3
And a logical sum circuit 31 for performing a logical sum of the output result of No. 3 and output to the processing circuit 30.