JP3225613B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a programmable timer built in a microcomputer.

[0002]

2. Description of the Related Art A programmable timer incorporated in a conventional microcomputer comprises, for example, a first counter 3 which counts up in synchronization with an input clock and a period of a timer operation as shown in a block diagram of FIG. And a comparator 2 that compares the values of the first counter 3 and the modulo register 1 and outputs a match signal if they match.

FIG. 4 shows the operation of a programmable timer built in a microcomputer of the prior art.
This will be described with reference to FIG.

FIG. 4 is a block diagram showing an example of a programmable timer in a conventional microcomputer, and FIG. 5 is a timing chart for explaining its operation.

When the timer is operated with the cycle of n,
First, n is set in the modulo register 1 by an instruction through the internal bus 4 (50 in FIG. 5), and a timer start instruction is executed (51 in FIG. 5). By executing this timer start instruction, the first counter 3 is initialized (the value of the first counter in FIG. 5 is 0). Thereafter, the first counter 3 counts up in synchronization with the clock.

The comparator 2 compares the contents of the first counter 3 with the contents of the modulo register 1 and outputs a coincidence signal if they match (52 in FIG. 5). When the first counter 3 overflows, it returns to the initial value "0" (53 in FIG. 5), sets the next value n + 1 in the modulo register 1 again (54 in FIG. 5), and executes the timer start instruction. (55 in FIG. 5), the first counter repeats counting up, compares the contents of the modulo register 1 with the contents of the count register, which is the first counter 3, and outputs a match signal if they match. (56 in FIG. 5).

Here, for example, in the case of an 8-bit timer,
The values that can be set in the modulo register 1 are 0 to FFH. Therefore, in order to perform a complete evaluation in the prior art, the above-described timer operation is performed 256 times with n = OFFH.

[0008]

In the conventional programmable timer built in the microcomputer,
The value of the modulo register could not be continuously changed automatically, and the only way to set the value in the modulo register was by an instruction.

Therefore, when the value of the modulo register is changed and evaluated, the value of the modulo register is reset by an instruction. For example, in the case of an 8-bit programmable timer, a timer operation is performed by sequentially setting values of 0 to FFH to the modulo register 256 times in order to perform a complete evaluation.

For this reason, the evaluation of the programmable timer
Value with the evaluation of other hardware of microcomputer
It is difficult to do it in parallelUWith disadvantagesI
You.

It is an object of the present invention to provide a microcomputer having a built-in programmable timer having a function of incrementing the value of a modulo register in synchronization with an overflow of a counter by eliminating the above-mentioned disadvantages. .

[0012]

Means for Solving the Problems The features of microcomputer of the present invention, CPU can execute the timer start command
Is reset by, and a counter for counting up in synchronization with the clock signal, and a logic circuit for outputting an increment signal from the overflow signal and the test signal of the counter, <br/> instruction execution of the only initial value CP U The values thereafter are set to coincide with each other by comparing the values of the modulo register having a counting function for holding the value counted up in synchronization with the increment signal with the values of the counter and the modulo register. a programmable timer consisting of a comparator which outputs a signal, the pre-SL CPU only to run two instructions initialization and timer start, before
In serial programmable timer, automatically and evaluated for all values which can be set to the motor-di Interview B register
It is to do it continuously .

[0013]

[0014]

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a programmable timer built in a microcomputer according to a first embodiment of the present invention.

A first counter 3 that counts up in synchronization with an input clock, a modulo register 1 that holds a value for determining a timer operation cycle, and a comparison between the value of the first counter 3 and the value of the modulo register 1 A comparator 2 that outputs a match signal if they match, and a second counter 5 that increments the value of the modulo register 1 in synchronization with the overflow signal of the first counter 3 during evaluation.
And a buffer 6 for setting the value of the second counter 5 in the modulo register 1 at the time of evaluation.

Next, the operation of the programmable timer built in the microcomputer of the first embodiment will be described.
This will be described with reference to a block diagram of the programmable timer shown in FIG. 1 and a timing chart for explaining the operation of the programmable timer shown in FIG.

First, at the time of evaluation, the test signal is activated, and the logic gates 7 and 8 and the buffer 6 are set to be able to receive the instruction start signal, the overflow signal and the output of the second counter 5, respectively. Next, an initial value is set from the internal bus 4 to the modulo register 1 (3 in FIG. 3).
0).

Next, a timer start instruction is executed (31 in FIG. 3). By executing this timer start instruction,
The first counter 3 and the second counter 5 are initialized to "0". Thereafter, the first counter 3 counts up in synchronization with the clock.

The comparator 2 compares the contents of the first counter 3 with the contents of the modulo register 1, and outputs a coincidence signal if they match (32 in FIG. 3). Further, the first counter 3 returns to the initial value "0" by the overflow signal and repeats counting up (33 to 35 in FIG. 3). This overflow signal causes the second counter 5 to count up and its contents to be set in the modulo register 1 via the buffer 6.

The operations after the initialization of the first counter 3 and the second counter 5 by the execution of the timer start instruction are repeated a predetermined number of times.

Accordingly, the test signal is activated, the initial value "0" is set in the modulo register 1, and all values that can be set in the modulo register 1 are automatically and continuously set by executing a start instruction. The test is performed.

That is, conventionally, the timer start command has to be executed again when the first counter 3 overflows. However, the timer start command need only be executed once as described above.

Next, a second embodiment will be described with reference to the drawings.

FIG. 2 is a block diagram of a programmable timer built in a microcomputer according to a second embodiment of the present invention.

According to FIG. 2, a first counter 3 counts up in synchronization with an input clock, and holds a value for determining a period of a timer operation, and counts in synchronization with an overflow signal of the first counter 3. A third counter (modulo register) 9 that increases, a comparator 2 that compares the values of the first counter 3 and the third counter (modulo register) 9 and outputs a match signal if they match, The third counter 9 according to the overflow signal
And a logic gate 10 for outputting an increment signal.

Next, the operation of the programmable timer built in the microcomputer of the second embodiment will be described.
This will be described with reference to FIGS.

First, at the time of evaluation, the test signal is activated and the gate of the logic gate 10 is opened. An initial value is set in a third counter (modulo register) 9 from a CPU (not shown) via the internal bus 4 (3 in FIG. 3).
0), and executes a timer start instruction (3 in FIG. 3).
1). By executing the timer start instruction, the first
Is initialized to "0".

Thereafter, the first counter 3 counts up in synchronization with the clock. The comparator 2 compares the content of the first counter 3 with the content of the third counter (modulo register) 9, and outputs a coincidence signal if they match (32 in FIG. 3). Further, the first counter 3 returns to the initial value "0" by the overflow signal and repeats counting up (33 in FIG. 3). The third counter (modulo register) 9 is counted up through the logic gate 10 by the overflow signal.

Therefore, the test signal is activated, and the third counter (modulo register) 9 stores the initial value “0”.
, And all the values that can be set in the third counter (modulo register) 9 are automatically and continuously evaluated simply by executing the start instruction.

In the second embodiment, the modulo register itself for holding the value for determining the period of the timer operation of the first embodiment is constituted by a third counter. That is, the functions of the second counter 5 and the modulo register 1 of the first embodiment are integrated. As a result, the hardware of one programmable timer can be reduced as compared with the first embodiment.

[0033]

As described above, the programmable timer incorporated in the microcomputer according to the present invention, upon evaluation, synchronizes with the overflow signal of the counter which counts up in synchronization with the input clock and sets the period of the timer operation. The value of the modulo register that holds the value that determines the value is counted up, so that all the values that can be set in the modulo register are automatically and continuously evaluated by simply activating the test signal and executing a start instruction. It can be performed.

For example, in the case of an 8-bit programmable timer, values that can be set in the modulo register are 0 to FF
This is 256 patterns of H. Therefore, in order to perform a complete evaluation, an instruction to set the value in the modulo
I had to do it 56 times.

However, in the present invention, the instruction for setting the value in the modulo register only needs to be executed once. This has an effect that the test pattern can be simplified.

Since the number of operations by instructions is reduced, the evaluation of the programmable timer can be easily performed in parallel with the evaluation of other hardware of the microcomputer.
This also has the effect of shortening the test time of the entire microcomputer and contributing to cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a timing chart of the programmable timer shown in FIGS.

FIG. 4 is a block diagram of a programmable timer of a conventional microcomputer.

FIG. 5 is a timing chart of the programmable timer shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 Modulo register 2 Comparator 3 First counter 4 Internal bus 5 Second counter 6 Buffer 7, 8, 10 Logic gate 9 Third counter (modulo register)

Claims (1)

(57) [Claims] [Claim 1] CPU is to run the timer start instruction
Is reset by Rukoto, and a counter for counting up in synchronization with the clock signal, and a logic circuit for outputting an increment signal from the overflow signal and the test signal of the counter, life <br/> old the only initial value CP U The value set by execution is the same as the value of the modulo register having a counting function for holding the value counted up in synchronization with the increment signal, and the values of the counter and the modulo register. a programmable timer consisting of a comparator which outputs a coincidence signal, the pre-SL CPU only to run two instructions initialization and timer start, the
In programmable timer, automatically and communicating the evaluation of all values that can be set in the mode di Interview B register
A microcomputer characterized by being performed continuously .