JPH02156343A - Tracer memory control circuit - Google Patents

Abstract

PURPOSE:To store only effective trace data by storing the counted value of a counting means as well together with the trace data to a trace memory. CONSTITUTION:When the condition of an FF 6 is 0, an address counter 7 is made incremental synchronously with a system clock. However, when the condition value is 1 and only when a microinstruction is executed, the count is made incremental and in the other case, the count is in a hold condition. Accordingly, the same address of a tracer memory 10 is still shown and trace data 4 are overwritten to the memory 10. While the condition value of a WATT signal 3 is 1, a counter 9 is made incremental synchronously with the system clock and when the condition value goes to 0, the counter 9 is reset. By adding the counter 9 to the trace information of the memory 10, it can be known of which clock the signal 3 is outputted before the microinstruction is executed. Then, the effective data can be stored to the memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracer memory control circuit, and more particularly to a tracer memory control circuit that stores the operation history of a CPU.

The tracer memory that stores the operating history of the CPU is controlled to increment the address counter in synchronization with the system clock and store the operating history of the CPU every clock during normal system operation. .

In this type of tracer memory control method, if the system is in a stall state or a state in which microinstruction execution is inhibited and this state continues for a long time, the address counter continues to be incremented by the clock during that time, so the tracer memory The trace data stored in the memory will have the same content, and the tracer memory will be filled with the same content. Therefore, there is a drawback that effective trace data necessary for subsequent analysis cannot be obtained.

1. Therefore, the present invention was made to solve the drawbacks of the prior art, and its purpose is to provide a tracer memory control circuit that can store only valid trace data. It's about doing.

According to the present invention, there is provided a tracer memory control circuit which stores trace data in a tracer memory by incrementing an address counter every clock in synchronization with a system clock, The tracer includes means for incrementing the address counter in synchronization with the timing when the specific condition is satisfied when the specific condition is satisfied, and a counting means for counting the period during which the specific condition is satisfied, and the count value of the counting means is also recorded together with the trace data. A tracer memory control circuit is obtained which is characterized in that the tracer memory control circuit is stored in a memory.

shakuhara week Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a tracer memory and a control circuit for the tracer memory according to an embodiment of the present invention, in which 1 is a microinstruction decode signal that is a set condition for the flip-flop 5, and 2 is a set condition for the flip-flop 5. The input signal from the operation panel of the electronic computer, 3 is the WA output when the execution of the microinstruction is inhibited.
4 is the trace data stored in the tracer memory, 5 is a flip-flop that can be set and reset from the microinstruction or the computer operation panel, 6 is the state value of the flip-flop 5 which is 1, and the WAIT signal A flip-flop that is valid while 3 is being output, 7
is an address counter of the tracer memory, 8 is a register for storing trace data to be stored in the tracer memory, and 9 is a register for storing trace data to be stored in the tracer memory.
is the WA output when execution of a microinstruction is inhibited.
A counter 10 is a tracer memory that counts how many clocks the IT signal has been output. Note that 11 indicates an OR gate, and 12 indicates an AND gate.

The flip-flop 5 is a flip-flop that indicates the trace condition of the tracer memory 10, and when the state value of the flip-flop 5 is 0, it indicates that the tracer memory 10 stores data every clock in synchronization with the system clock. When the state value is 1, it indicates that the tracer memory 10 stores data only when a microinstruction is executed.
．． It is possible to reset the settings from the fi operation panel.

Flip-flop 6 has the state value of flip-flop 5 equal to 1.
When the trace condition of the tracer memory 10 is set to a mode in which data is stored only when executing a microinstruction, when the WAIT signal 3, which is output when the execution of a microinstruction is inhibited, is output, the state value changes. When the state value of the flip-flop 6 is 1, the update of the address counter 7 of the tracer memory 10 is inhibited. In other words, the address counter 7 is the flip-flop 6
When the state value is 0, the count is incremented in synchronization with the system clock, but when the state value is 1, the count is incremented only when a microinstruction is executed; otherwise, it is in a hold state, and the tracer memory 10
remains indicating the same address, and the trace data 4 is overwritten in the tracer memory 10.

Counter 9 indicates that while the execution of the microinstruction is inhibited,
This is a counter that counts how many lock periods the WAIT signal 3 is output. While the state value of the WAIT signal 3 is 1, it is incremented in synchronization with the system clock, and the state value becomes 0. sometimes reset. By adding this counter 9 to the trace information in the tracer memory 10, it becomes possible to know how long the WAIT signal 3 was output for 17 times before the microinstruction was executed.

As described in detail, according to the present invention, the trace condition of the tracer memory is normally set to a mode in which data is stored every clock in synchronization with the system clock, and is used for debugging when the system stalls. By switching to a mode in which data is stored only when a microinstruction is executed, only the data when the microinstruction is executed is stored in the tracer memory, and the count number of the WA I T signal is also stored in the tracer memory. This makes it possible to know how many clocks the WAIT signal was output before the microinstruction is executed, and the effect is that even if the capacity of the tracer memory is small, data useful for analysis can be stored in the memory. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 5.6...Flip-flop 7...Address counter 9...Counter 10... Tracer memory Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) A tracer memory control circuit that stores trace data in a tracer memory by incrementing an address counter every clock in synchronization with a system clock, and when a predetermined specific condition is satisfied, The method includes means for incrementing the address counter in synchronization with timing, and a counting means for counting the period during which this specific condition is satisfied, and the count value of this counting means is also stored in the tracer memory together with the trace data. Features a tracer memory control circuit.