JPH0797340B2 - Tracer memory control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tracer memory control circuit, and more particularly to a tracer memory control circuit that stores an operation history of a CPU.

2. Description of the Related Art A tracer memory that stores the operation history of a CPU is controlled so as to store the operation history of each clock CPU while advancing the address counter in synchronization with the system clock during normal system operation.

In such a tracer memory control method, when the system is in a stalled state or in a state where micro instruction execution is suppressed and this state continues for a long time, the address counter continues to be stepped by the clock during that time. The contents of the trace data stored in the memory become the same contents, and the tracer memory is filled with the same contents. Therefore, there is a drawback that effective trace data required for the subsequent analysis cannot be obtained.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the drawbacks of the prior art, and an object of the present invention is to provide a tracer memory control circuit capable of storing only effective trace data. It is in.

According to the present invention, there is provided a tracer memory control circuit which increments an address counter at a predetermined timing to store trace data in a tracer memory, which is synchronized with a system clock as the predetermined timing. And a count unit for counting the number of clocks while the execution of the microinstruction is suppressed, and a unit for selecting one of the mode and the mode synchronized with the execution of the microinstruction, A tracer memory control circuit is obtained in which the output of the counting means is stored in the tracer memory.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block of a tracer memory and a control circuit of the tracer memory according to an embodiment of the present invention. In the figure, 1 is a decode signal of a microinstruction that is a set condition for the flip-flop 5, 2 is an input signal from the operation panel of the computer that is a set condition for the flip-flop 5, and 3 is an output when the execution of the microinstruction is suppressed. WAIT signal, 4 is trace data stored in the tracer memory,
5 is a flip-flop that can be set / reset from a microinstruction or an operation panel of an electronic computer, 6 is a flip-flop whose state value is 1 and the WAIT signal 3 is valid, and 7 is a flip-flop. Address counter of the tracer memory, 8 is a register for storing trace data to be stored in the tracer memory, 9 is a counter for counting how many clocks the WAIT signal is output when the execution of the micro instruction is suppressed, 10 is a tracer memory. Incidentally, 11 is an OR gate and 12 is an AND gate.

The flip-flop 5 is a flip-flop indicating the trace condition of the tracer memory 10. When the state value of the flip-flop 5 is 0, it indicates that the tracer memory 10 stores clock data in synchronization with the system clock. A value of 1 indicates that the tracer memory 10 stores data only when executing a microinstruction. This flip-flop 5 can be set / reset from a micro instruction or an operation panel of an electronic computer.

The state value of the flip-flop 6 is 1
Is output when the trace condition of the tracer memory 10 is set to a mode for storing data only when the micro instruction is executed, and when the execution of the micro instruction is suppressed.
When the WAIT signal 3 is output, the state value 1 is shown. When the state value of the flip-flop 6 is 1, updating of the counter of the address counter 7 of the tracer memory 10 is suppressed. That is, when the state value of the flip-flop 6 is 0, the address counter 7 is incremented in synchronization with the system clock, but when the state value is 1, the count is incremented only when a micro instruction is executed, and other than that. Becomes a hold state, the same address of the tracer memory 10 is still shown, and the trace data 4 is written in the tracer memory 10.

The counter 9 keeps displaying while the execution of the micro instruction is suppressed.
It is a counter that counts how many clocks the output WAIT signal 3 has been output. When the state value of the WAIT signal 3 is 1, the counter is incremented in synchronization with the system clock and the state value becomes 0. Is reset to. By adding the counter 9 to the trace information of the tracer memory 10, it becomes possible to know how many clocks the WAIT signal 3 has been output before the microinstruction is executed.

EFFECTS OF THE INVENTION As described above, according to the present invention, the trace condition of the tracer memory is normally used in the mode in which each clock data is stored in synchronization with the system clock. By switching to the mode that stores data only when the micro instruction is executed, only the data when the micro instruction is executed is stored in the tracer memory, and by further storing the count number of the WAIT signal in the tracer memory, It becomes possible to know how many clocks the WAIT signal has been output before the execution of the micro instruction, and it is possible to store the data effective for analysis in the memory even if the tracer memory has a small capacity.

[Brief description of drawings]

 FIG. 1 is a block diagram of an embodiment of the present invention. Explanation of symbols of main parts 5,6 ...... Flip-flop 7 ...... Address counter 9 ...... Counter 10 ...... Tracer memory

Claims (1)

[Claims] 1. A tracer memory control circuit in which an address counter is incremented at a predetermined timing to store trace data in a tracer memory, wherein a mode and a micro instruction synchronized with a system clock are used as the predetermined timing. It has a means for selecting one of the modes synchronized with the execution and a counting means for counting the number of clocks while the execution of the microinstruction is suppressed, and outputs the output of the counting means together with the trace data. A tracer memory control circuit for storing in the tracer memory.