JP2583354B2 - Data comparator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data comparator for comparing the magnitude of two digital data.

[Conventional technology]

Conventionally, as shown in FIG. 4, this type of data comparator includes a register 21 for storing one of two data, a register 22 for storing the other data, a full adder and the like. , A register 24 that latches microcode, and a programmable logic array (hereinafter, referred to as ALU) that generates control signals for controlling the registers 21, 22, and ALU23 based on the contents of the microcode. Hereinafter referred to as PLA) 2
5 and first, register 21 to ALU23
To the data bus 26, and then outputs the data of the register 22 to the data bus 26. The other data on the bus transfers the data stored in the register 21
By subtracting one of the data from register 21 and taking care of the resulting carry-out 27.
Compared the size of the two data stored in the 22 and the.

[Problems to be solved by the invention]

The above-described conventional data comparator executes the subtraction function of the ALU according to the microcode instruction and determines the magnitude of the two data based on the carry out.
A total of about 5 machine cycles (two or more times depending on the number of bits of data to be compared and the number of bits of the ALU) are required to perform data transfer from the register group to the ALU and subtraction, which is a burden on software program development. In addition, depending on the signal to be processed, there is a disadvantage that all processing cannot be executed within the allowable processing time and an overflow may occur.In addition, since microcode increases, microcode software must be used. There is a disadvantage that the memory space of the instruction ROM to be stored becomes large.

[Means for solving the problem]

The data comparator of the present invention comprises a two-phase first and second phase comparator.
, And an input signal of an operation start command having a pulse width of one cycle of the second clock and n cycles of the second clock when the data to be compared is n bits (an integer of n1). First and second data registers for receiving two n-bit data to be compared, each of which is input with a second input signal having a pulse width of one minute and having a designated number of bits; The first and second AND gates of the first and second input signals and the first clock respectively accumulate data from the second data register serially from the most significant bit. 2 shift registers, an exclusive OR gate for detecting a mismatch of each bit from the first and second shift registers,
A first latch circuit for latching the second input signal;
A second latch circuit for latching the first input signal with the first clock, a third latch circuit for latching the output of the second latch circuit with the second clock, A first D-type flip-flop that holds an output signal of a gate by an output of a third AND gate of the output signal of the first latch circuit and the second clock, and an output of the first flip-flop A set / reset flip-flop which is reset by a signal and is set by an output signal of the third latch circuit; and three of an output signal of the set / reset flip-flop, an output signal of the first latch circuit, and the second clock. Third AND of input
A second flip-flop that holds an output signal of the first shift register with an output signal of a gate and outputs a comparison determination of the two n bits to a comparison determination terminal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG.

In FIG. 1, this embodiment uses two-phase clocks φ ₁ and φ _2.
In work, and LOAD13 input signal having a pulse width of one period of the clock phi _2, data is n-bit (integer n1)
In the case of (1), a data register (hereinafter referred to as REG) 1, 2 is supplied with an input signal SHIFT 14 having a pulse width of n cycles of the clock φ ₂ and storing two n-bit data to be compared. And each data from REG1,2
LOAD13 and the SHIFT14 clock phi ₁ and of the AND gates 16 and 17 (hereinafter referred to as SHR) shift register slide into storage from the most significant bit (MSB) to the serial 3, 4, SH
An exclusive OR gate (hereinafter referred to as EXOR) 5 for detecting a mismatch of the square bits from R3 and R4, a latch circuit (hereinafter referred to as LA) 6 for latching SHIFT14, and LA10 and 9 for latching LOAD13.
If, (hereinafter referred to as DFF) D-type flip-flop for holding the output of the AND gate 18 between the output signal and the clock phi ₂ of LA6 an output signal of EXOR5 and 7, reset by the output signal of DFF7 LA9 output signal A set / reset flip-flop (hereinafter, referred to as RSFF) 8 to be set by RSFF8
And outputs the held comparison determination of the two data output signals of SHR3 the output signal of the AND gate 11 of the three inputs of the output signals of LA6 and the clock phi ₂ to the comparison determination terminal 15 DFF1
2 and so on.

Next, the operation of this embodiment will be described with reference to FIGS.

When LOAD13 becomes active, SHR3 and 4 load the data from REG1 and REG2, and when SHIFT14 becomes active, output the loaded data with the most significant bit (MSB) first and output each of the data input by EXOR5. detecting a bit mismatch, the result is the clock phi ₁ LA6, the aND gate 1
8 by being stored in DFF7 clock phi ₂ of timing delayed one period to SHIFT14.

Meanwhile, RSFF8 is, LOAD13 is set becomes active clock phi ₂ one cycle delay, since the clock phi input terminal of the DFF12 in the enabled state, the SHIFT14 becomes active, RSFF8 outputs of SHR3 until reset Data is stored by DFF12.

RSFF8 is reset when EXOR5 becomes active, that is, when the output data from SHR3, 4 does not match, and when it detects that the data of REG1, 2 is not equal at this time. Then, the data of SHR3 at that time is stored in DFF12, and then RSFF8 is reset to inhibit the input of the clock φ to DFF12.

As described above, after the shift of the two data is completed, that is, after the SHIFT 14 becomes inactive, the comparison determination terminal 15 is taken care of. However, when the n-bit data of REG1, 2 is the same, the DFF 12 becomes SHR3, that is, REG1 Of the comparison determination terminal 15 is 1 or 0
Which one is selected depends on the least significant bit (LSB) of the data, but since the data is equal, either data may be selected. When the data of REG1 is larger than that of REG2, the data of the i-th bit shown in FIG. 2 always becomes 1 and 0, respectively. Becomes 1 and the clock to DFF12 is prohibited.
Flag to select. Conversely, when REG2 is larger, the output of the comparison determination terminal 15 becomes 0.

FIG. 3 is a diagram showing an example of data stored in the two REGs shown in FIG.

1, 2 and 3, when the data shown in FIG. 3 is stored in REG 1 and REG 2, as shown in FIG.
The determination of (REG1 data)> (REG2 data) is made in the bit, and the output of the comparison determination result is held in DFF12.

〔The invention's effect〕

As described above, according to the present invention, two digital data are serially compared in magnitude from the most significant bit (MSB) in a bit unit, and a flag of a comparison determination result is generated. This has the effect of reducing the development burden, shortening the processing time, and reducing the memory space of the instruction ROM for microcode. Also, comparing the conventional data with the ALU, it is possible to compare the carrier when performing other calculations. However, the present invention has an effect that an output signal from the comparison determination result terminal can be used as a comparison flag until another data is compared.

Further, in the present invention, the comparison is performed after accumulating the two data to be compared in the first and second registers, respectively. Therefore, the comparison operation is performed using the first and second clocks independent of the speed of the two data. Is effective.

Furthermore, by the second input signal specifying the number of bits,
The number of consecutive bits in the respective data stored in the first and second registers can be specified, and the first input signal and the first or second clock cause the logical value of this data to be changed for the first time. Since the position of a different bit can be known, and the result of comparison of the data can be known from the output of one second flip-flop, the processing on the side using this output signal can be facilitated. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of this embodiment shown in FIG. 1, and FIG. 3 is stored in two REGs shown in FIG. FIG. 4 is a block diagram showing an example of data, and FIG. 4 is a block diagram showing a conventional data comparator. 1,2,21,22 ... data register (REG), 3,4 ... shift register (SHR), 5 ... exclusive OR gate (EXO
R), 6, 9, 10 ... Latch circuit (LA), 7, 12 ... D type flip-flop (DFF), 8 ... Set-reset type flip-flop (RSFF), 13 ... Input signal (LOA
D), 14: Input signal (SHIFT), 15: Comparison judgment terminal,
27 Carrier out terminal, 11, 16, 17, 18 AND gate,
24 …… Microcode latch register (REG), 23 ……
Arithmetic operation circuit (ALU), 25 Programmable logic array (PLA), 26 Data bus.

Claims (1)

(57) [Claims] 1. The method according to claim 1, wherein the first and second clocks operate on two phases.
The data to be compared with the input signal of the operation start command having a pulse width of one cycle of the second clock is n bits (n ≧ n).
In the case of (an integer of 1), a second input signal having a pulse width of n cycles of the second clock and having a designated bit number is input, and two n-bit data to be compared are stored respectively. First and second data registers and respective data from the first and second data registers are converted to first and second input signals and the first clock by the first clock;
And a first and second shift register that serially accumulates from the most significant bit by an AND gate, and an exclusive OR gate that detects mismatch of each bit from the first and second shift registers. A first latch circuit for latching the second input signal, a second latch circuit for latching the first input signal by the first clock, and an output of the second latch circuit to the second latch circuit. And a third latch circuit that latches the output signal of the exclusive OR gate and an output signal of the third AND gate between the output signal of the first latch circuit and the second clock.
A first flip-flop of a type, a set / reset flip-flop reset by an output signal of the first flip-flop and set by an output signal of the third latch circuit; an output signal of the set / reset flip-flop; The output signal of the first shift register is held by the output signal of the third AND gate having three inputs of the output signal of the first latch circuit and the second clock, and the two n
And a second flip-flop for outputting a bit comparison judgment to a comparison judgment terminal.