JP2845662B2 - Peak / bottom hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak / bottom hold circuit, and in particular, compares a plurality of bits of data transmitted serially for each frame in bit units and sequentially updates large or small data. It relates to a peak / bottom hold circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of peak / bottom hold circuit performs serial-to-parallel conversion of external input serial data 14 of an input terminal 1 as shown in FIG.
Conversion) circuit 13, an arithmetic operation circuit (ALU) 18 composed of a full adder, etc., a register 9 for latching a microcode, and the contents of the microcode.
The circuit includes a / P conversion circuit 13 and a programmable logic array (PLA) 10 for generating a control signal for controlling a register 15 for holding data after comparison.

[0003] First, in the S / P conversion circuit 13, the serial DATA 14 is converted from serial to parallel, then transferred to the ALU 18 via the data bus 16, and then stored in the register 15 until the previous frame. / Minimum data is transferred to the ALU 11 via the data bus 16, subtracted from the data transferred from the S / P conversion circuit 13 already stored in the ALU 18, and the resulting carry-out 12 is taken care of. Peak / bottom hold is performed by judging the magnitude and transferring either data to the register 15 as update data.

[0004]

The above-described conventional peak / bottom hold circuit uses a microcode instruction.
Execute the subtraction function of ALU18,
2 is used to determine whether the size is large or small.
A total of about 5 machine cycles to execute data transfer and subtraction to U18 (the number of bits of relatively
(More than twice the processing time depending on the number of bits of 8), and there is a drawback that a load is required for software program development.

[0005] In addition, depending on the signal to be processed, there is a disadvantage that all the processing cannot be executed within the allowable processing time and an overflow may occur. Further, since the microcode is increased, an instruction for storing microcode software is required. The disadvantage is that the memory space of the ROM is large, and a new ALU is required to realize this function.
However, there is a drawback that the circuit scale becomes very large when the configuration such as 11 or PLA10 is configured.

An object of the present invention is to provide a peak / bottom hold circuit which solves the above-mentioned drawbacks and can perform necessary processing within an allowable processing time even if the circuit scale is small.

[0007]

A peak / bottom hold circuit according to the present invention comprises a shift register circuit for storing serially input data, and an output of the shift register and serial data input from the outside. An exclusive-OR circuit that compares the bits of the same order and compares the data bits on the external input serial data side when the value of the shift register circuit differs from that of the external input serial data by the output of the exclusive-OR circuit. A D-type flip-flop circuit with reset, a circuit for generating the clock input signal, and a clock input signal generated once in one frame of the externally input serial data until a clock of the next frame is input. A D-type flip-flop circuit with a set for inhibiting generation and a shift register circuit; Characterized by comprising a selector for selecting data to be force.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the present embodiment shown in FIG.

In FIG. 1, in this embodiment, a clock φ and an external serial data input (hereinafter referred to as “DATA”) 11 input in MSB first, a clock CK for shifting DATA 11 at the falling edge, and a start indicating a frame break of DATA 11 are shown. Operated by signal 2, DATA11 and 1
Exclusive OR (EOR) 3 for comparing with a shift register (SR) 8 that sequentially holds the peak / bottom data for each bit before the frame, and when there is a bit in which the output of DATA 11 and SR 8 do not match. , A D-type flip-flop with reset (RDFF) 5 for holding bit data on the DATA 11 side, and if there are mismatched bits in the outputs of DATA 11 and SR8, only one clock is input to RDFF 5 with a bit having a higher bit order. ,
In the subsequent bits, a logical product (hereinafter referred to as AND) 4 for inhibiting clock input, a D-type flip-flop circuit with set (SDFF) 6 set by the start signal 2,
When the output of the RDFF5 is "1", DATA11 is
In addition, a selector 7 that outputs the output of the SR 8 when it is “0” is provided.

Next, the operation of this embodiment will be described with reference to FIGS.

The data DADA1 is constituted by i (i ≧ 1) bits, the peak data mi of one frame before is held in SR8, and the data ni of the new frame is stored in DATA1.
Is input, ni = mi, up to the (i-1) th bit.
ni-1 = mi-1, and ni-2 at the (i-2) th bit
> Mi-2, that is, ni> mi will be described.

When the start signal (START) 2 becomes active, the SDFF 6 and the RDFF 5 are set and reset, respectively, the AND 4 is in a clock generation enable state, and the selector 7 is in a state of inputting the output of the SR 8 to the SR 8.

Up to the i-2th bit, DATA1 and SR
8 are the same, and EOR3 is non-active, so that no clock is input to RDFF5,
Since the output of the FF 5 holds the reset state “0” and the selector 7 selects the output of the SR 8 so as to be input to the SR 8, mi and mi−1 are sequentially held in the SR 8 at the falling edge of the clock CK. . At the falling edge of this clock CK,
When the next data bits ni-2 and mi-2 are input to EOR3, ni-2> mi-2 (that is, ni-2 =
1, mi-2 = 0), the output of EOR3 is CK
It becomes "1" for one cycle, and holds and outputs ni-2 (= 1) which is the bit data of DATA11 to the RDFF5 at the rise of the clock φ in that period, and the selector 7 sets ni to
-2 is output, and ni-2 is held in SR8 at the next falling edge of CK.

The output of EOR3 is "1" for one cycle of CK.
AND4 becomes “1” at the clock φ in that period, but the clock φ falls and AND4 becomes “1” →
When the signal falls to “0”, the SDFF 6 outputs “0” at the falling edge, so that the clock generation of AND4 is disabled, and the RDF is disabled until the next START2 becomes active.
No clock is input to F5, and as in the (i-4) th bit, even if ni-4 <mi-4, the RDFF5 remains in the ni-2 (= 1) state held in the (i-2) th bit. Inputs data ni on the DATA11 side to SR8.

As described above, the data bits are sequentially compared and determined.
The peak hold is performed by switching the input of.

In the case of bottom hold, S
(Select control signal) Invert input or J0,
By replacing J1 (data-in input) and changing ni to be output when ni> mi, bottom hold is realized.

[0017]

As described above, according to the present invention, the serially input data and the stored peak / bottom data are compared serially, and the data is selected, so that the signal processing can be performed in comparison with the prior art. This has the effect of reducing the software program development burden, reducing the processing time, reducing the memory space of the microcode instruction ROM, and reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a peak / bottom hold circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional peak / bottom hold circuit.

[Explanation of symbols]

 Reference Signs List 1 serial data input terminal 2 start signal indicating start of frame 3 exclusive OR (EOR) 4 logical product (AND) 7 selector 8 shift register 9, 15 register 10 programmable logic array (PLA) 11 external serial data input 13 serial / Parallel conversion circuit 18 arithmetic operation circuit (ALU)

Claims (1)

(57) [Claims] A shift register circuit for storing serially input data; an exclusive OR circuit for comparing an output of the shift register with serial data input from the outside in correspondence with bits having the same order; A D-type flip-flop circuit with reset for holding a data bit on the external input serial data side when the value of the shift register circuit differs from the value of the external input serial data by an output of an exclusive OR circuit; A circuit for generating a clock input signal of a circuit, and a D-type flip-flop with a set for prohibiting clock generation until data of the next frame is input when the clock input signal is generated once in one frame of the externally input serial data And a selector for selecting data to be input to the shift register circuit. And a peak / bottom hold circuit.