JP3259489B2 - Decimal divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal divider.

[0002]

2. Description of the Related Art FIG. 6 is a conceptual diagram of a conventional decimal divider. Conventionally, a decimal divider repeatedly subtracts a divisor from a dividend, and when the remainder becomes negative, a value obtained by subtracting 1 from the number of repetitions up to that point is used as a quotient (partial quotient) of the digit, and is excessively subtracted. The divisor is added to the dividend to obtain the remainder (partial remainder) of one digit, and then the partial quotient and the partial remainder are shifted left by one digit (10 times). Basically, the subtraction of the divisor from the remainder and the correction of excessive subtraction are repeated several times. As an improved type, there is a partial quotient prediction method. This utilizes the fact that the value of one digit of the partial quotient can be predicted with an error of 1 or less from the upper several digits of the dividend and the upper several digits of the divisor. A numerical value having a large value in the prediction range is used as a predicted partial quotient, and the value of the predicted partial quotient of the divisor is subtracted from the partial remainder. If the resulting remainder is negative, the correction is made by a factor of one. This is basically the same as division by hand. For example, 1 times, 2 times, 4 times, 8 times divisor
A double is created in advance and set in the divisor holding circuit 3 (or generated from the divisor).
This is a method of performing subtraction by combining doubling, quadrupling, and doubling. For example, assuming that the predicted partial quotient is 7, four times, twice and one times the divisor of the divisor holding circuit 3 are sequentially selected and subtracted from the contents of the partial remainder (dividend) register 1. As a result, only three times are required for seven times when the divisor is repeatedly repeated and subtraction is performed, and there are cases where the prediction is correct and excessive correction is not required, thereby increasing the speed. However, this still requires a maximum of three subtractions per digit, and the correction of overdraw is required with about half the probability.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to realize a high-speed decimal divider by reducing the number of times a multiple of a divisor per digit is reduced and reducing the probability of overdrawing correction. I have.

[0004]

FIG. 1 is a block diagram showing the principle of the present invention. At first, it holds the input decimal dividend,
A partial remainder register 1 for holding a partial remainder generated for each operation cycle, a divisor register 2 for holding an input decimal divisor, a divisor generating circuit 3 for generating a multiple of the content of the divisor register, From the contents of the remainder register 1,
The output of the divisor generating circuit 3 is subtracted to obtain a partial remainder register 1
A partial remainder arithmetic circuit 4 mainly composed of a decimal adder, which is shifted in, and a one-digit partial quotient is calculated from the value of the upper digit of the output of the partial remainder arithmetic circuit 4 and the value of the upper digit of the divisor register 2. A partial quotient prediction circuit 5 for predicting, a predicted partial quotient holding register 6 for holding the predicted partial quotient, and a partial remainder operation circuit 4
A partial quotient correction circuit 7 for correcting the partial quotient by -1 according to the sign of the output of, and setting the quotient in a quotient register, and a control circuit 9 for controlling the whole. , And subtracts the divisor from the partial remainder, corrects the partial remainder and the partial quotient by the sign of the output of the partial remainder calculation circuit 4, and obtains a partial quotient for each decimal digit by a divider. Some points are the same as before.

According to the present invention, the divisor generating circuit 3 uses the divisor 1
A double, a quadruple, a quadruple, a sixfold, and an eightfold value, that is, a value that is an even multiple of the divisor in addition to the divisor itself, and whether the content of the predicted partial quotient holding register 6 is an odd number other than 1 Is provided.

The control circuit 9 performs an operation cycle for each digit,
When the predicted quotient is 1 or even according to the output of the odd / even judgment circuit 10, the partial remainder operation circuit 4 subtracts the predicted quotient multiple of the divisor from the content of the partial remainder register 1 to obtain the partial remainder register 1.
If the sign of the subtraction result is positive, the contents of the predicted partial quotient holding register 6 are shifted into the quotient register 8 and the operation proceeds to the next digit operation cycle. If the sign of the subtraction result is negative, the auxiliary operation cycle is started. Then, one time of the divisor is added to the content of the partial remainder register 1 and the content of the predicted partial quotient holding register 6 is decremented by one and input to the quotient register 8. When the predicted quotient is an odd number other than 1, the prediction of the divisor is performed. The quotient minus one is subtracted and set in the partial remainder register 1, the auxiliary operation cycle is started, one time of the divisor is subtracted, and if the sign of the subtraction result is positive, the result is set in the partial remainder register 1. The contents of the predicted partial quotient holding register 6 are shifted and input to the quotient register 8, and if the sign of the subtraction result is negative, the contents of the partial remainder register 1 are not updated. Quotient register 8 Configured to determine the quotient by reset input.

Instead of generating the divisor directly from the divisor register 2 by the divisor generating circuit 3, a divisor holding circuit is provided, and a value of an even multiple of the divisor is written to the partial remainder operation circuit 4 prior to the division operation processing. , And the result may be held.

[0008]

FIG. 2 shows a summary of the predicted values of the partial quotients and the explanation of the processing. When the partial quotient prediction value is 0 or 1, the value is selected as a multiple of the divisor, and the operation ends in one cycle. Even when the partial quotient predicted value is an even number, the value is selected as a multiple of the divisor and subtraction is performed in the first cycle, and if the sign of the result is positive, the process is similarly terminated. If the sign of the result is negative, the auxiliary cycle is started, the excessively subtracted one is added, and the partial quotient predicted value is also reduced by -1 to make it a fixed partial quotient.

If the partial quotient predicted value is an odd number other than 1, 1
The even number that is as small as possible is selected as a multiple of the divisor, and the subtraction is performed in the first cycle. In this case, since the value smaller than the predicted quotient by 1 is used, the sign of the result is always positive. Activate the auxiliary cycle and subtract the remaining one, and if the result is positive, the result is correct; if negative, the result is too much. Since the amount of overdrawing in the case of a negative value is determined to be one time the divisor, the correct partial remainder can be left in the partial remainder register 1 by prohibiting the result from being set in the partial remainder register 1. Therefore, there is no need to start an auxiliary cycle for correction. The predicted partial quotient is corrected by −1.

As described above, division can be processed in one or two cycles per digit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of an embodiment of the present invention. Those having the same functions as those in FIG. 1 are denoted by the same reference numerals.

In the figure, a divisor generating circuit 3 includes a logic circuit for generating two digits of double, four times, six times, and eight times for each digit of the divisor register 2, a logic circuit for converting to a complement thereof, and It consists of an output selection circuit. The 2 digits of the multiple output are the upper C
And the lower-order S, and the conversion to the complement is performed for each digit. As a result, the divisor generating circuit 3 stores the divisor register 2
0 times, +1 times, -1 times, -2 times, -4 times, -6 times the contents of
The output of doubling and -8 times is output as two numbers divided into an upper value C and a lower value S. The output multiple is determined by the control circuit 9
Selects according to the predicted partial quotient holding register 6.

The three-input decimal adder 4 is a partial remainder arithmetic unit, and adds the output of the partial remainder register 1 and the two outputs of the divisor generation circuit 3. If the two outputs of the divisor generation circuit 3 are complements, the result is a subtraction process. This three-input decimal adder may be configured in any manner, but if it is configured like the decimal adder disclosed in Japanese Patent Application No. 5-300711, the speed can be increased.

The control process basically solves the problem except that a backup register 6b of a predicted partial quotient holding register is provided to speed up processing of the next digit when the predicted quotient is an odd number. This is the same as that described in the section of the means and operation. An example of calculation of specific numerical values will be described with reference to the time chart of FIG. 4 and the calculation example of FIG. Hereinafter, the contents of the register and the adder are expressed left-justified.

First, it is assumed that 2468 is set as the dividend in the partial remainder register 1 and 208 is set in the divisor register 2. Output 2 of partial remainder arithmetic unit (adder)
The next partial quotient is predicted to be 1 from the upper digit of 468 and the contents 208 of the divisor register 2. In operation cycle 1, predicted partial quotient holding register 6
Is 1 so that 208 × 1 = 208 is subtracted from the partial remainder register 1 and 388 is set in the partial remainder register 1. Output 388 of partial remainder arithmetic unit (adder)
And the next partial quotient prediction value is predicted to be 1 from the upper digit of the contents 208 of the divisor register 2. In operation cycle 2, similarly, 208 × 1 = 208
Is subtracted from the partial remainder register 1 and 1880 is set in the partial remainder register 1. Partial remainder arithmetic unit (adder)
From the output 1800 of the divisor register 2 and the upper digit of the content 208 of the divisor register 2, the next partial quotient prediction value is predicted to be 9. In operation cycle 3, predicted partial quotient holding register 6
Is 9 (odd number), so that 208 × 8 = 1664
Is subtracted from the partial remainder register 1, and 136 is set in the partial remainder register 1. The predicted value of the partial quotient of the next digit is 6
And is held in the backup register 6b of the predicted partial quotient holding register. In operation cycle 4, an auxiliary cycle is started. In the operation cycle 4, 201 × 1 = 2 from the output 136 of the partial remainder operation unit (adder)
08 is subtracted to a negative value -72. This result is not set by closing the partial remainder register 1 input gate. In addition, the backup register
Transfer the value of 6b. Therefore, the value obtained in operation cycle 3 is retained as the partial remainder and the predicted value of the partial quotient of the next digit. In the operation cycle 5, the predicted partial quotient holding register 6
Is 6 (even number), 208 × 6 = 1248
Is subtracted from the partial remainder register 1, and 1120 is set in the partial remainder register 1. No correction is needed because the result is positive. The predicted value of the partial quotient of the next digit is predicted to be 5. In operation cycle 6, predicted partial quotient holding register 6
Is 5 (odd number), 208 × 4 = 832 is subtracted from the partial remainder register 1, and 2880 is set in the partial remainder register 1. Predicted value of partial quotient of next digit is 4
Is set in the backup register 6b of the predicted partial quotient holding register. An operation cycle 7 is started as an auxiliary cycle. In the operation cycle 7, 201 × 1 = 208 is subtracted from the output 288 of the partial remainder register to obtain a positive value +80. In this case, operation cycle 4
Unlike this, the input gate of the partial remainder register 1 is opened to update the value. Further, the predicted value 4 of the partial quotient of the next digit is set in the predicted partial quotient holding register 6 from the backup register 6b. In the operation cycle 8, the predicted partial quotient holding register 6
Is 4 (even number), 208 × 4 = 832 is subtracted from the partial remainder register 1 and −32 is set in the partial remainder register 1. Since the result is negative, it needs to be corrected, and the operation cycle 9 is started as an auxiliary cycle. In the operation cycle 9, the output of the partial remainder register -3
By adding 201 × 1 = 208 to 2 and correcting for excessive pulling, a positive value 176 is obtained. The partial quotient also performs -1 correction. Hereinafter, the calculation is performed in the same manner.

In this way, every time a fixed partial quotient is obtained, it is shifted into the quotient register 8, and 11865 is input.
The value of 3 ... remains.

[0017]

As described above, according to the present invention, 1
In the zero-base division, a high-speed divider capable of performing one or two cycles per digit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is an explanatory diagram of partial quotient prediction values and processing

FIG. 3 is a configuration diagram of an embodiment.

FIG. 4 is a time chart of the embodiment.

FIG. 5 Operation example

FIG. 6 is a conceptual diagram of a conventional decimal divider.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 partial remainder register 2 divisor register 3 divisor generating circuit (divisor holding circuit) 4 partial remainder arithmetic circuit (decimal adder) 5 partial quotient prediction circuit 6 predicted partial quotient holding register 6 b backup register 7 partial quotient correction circuit 8 quotient Register 9 control circuit 10 odd / even judgment circuit

Claims (2)

(57) [Claims] 1. A partial remainder register that initially holds an input decimal dividend and holds a partial remainder generated in each operation cycle, a divisor register that holds an input decimal divisor, and a divisor. 1x, 2x, 4x, 6x, 8x of register contents
The divisor generation circuit that generates the divisor and the content of the partial remainder register select the divisor generation circuit.
Adds and subtracts the output and shifts it into the partial remainder register.
Prediction portion holding the parts partial remainder calculation circuit that, the upper digit value of the output of the partial remainder calculation circuit, and its output partial quotient prediction circuit for predicting the order of magnitude of the partial quotient from the upper digit value of the divisor register A quotient holding register , a partial quotient correction circuit for correcting the predicted partial quotient by -1 and an odd / even determination for determining whether the predicted partial quotient is an odd number other than 1
Circuit , a quotient register for holding the quotient of the operation result, and a control circuit for controlling the whole, wherein the control circuit performs the scaling according to the value of the predicted partial quotient in the operation cycle for each digit.
The divisor obtained by selecting the output of the number generator is calculated from the partial remainder
Subtraction, in accordance with the output of the parity judgment circuit, the predicted partial quotient is 1 or when an even number, the contents of the sign of the subtraction result is positive if the predicted partial quotient holding register and shift to the quotient register to the next digit of the operation cycle If the sign of the subtraction result is negative, start the auxiliary operation cycle,
One time of the divisor is added to the contents of the partial remainder register, and the prediction unit
The content of the quotient holding register is decremented by 1 and shifted into the quotient register. When the predicted quotient is an odd number other than 1, the divisor (predicted partial quotient−
1) Subtract the doubled number and input it to the partial remainder register, start the auxiliary operation cycle, subtract 1 times the divisor, and if the sign of the subtraction result is positive, set the subtraction result in the partial remainder register and predict Shift the contents of the partial quotient holding register into the quotient register, and update the contents of the partial remainder register if the sign of the subtraction result is negative.
Without the determined quotient by controlling so as to shift input to the quotient register decrements the contents of the prediction partial quotient holding register
Decimal divider Mel. 2. The apparatus according to claim 1, wherein a divisor holding circuit is provided instead of the divisor generating circuit, and a numerical value of an even multiple of the divisor is held prior to arithmetic processing.
Decimal divider.