JPH02165326A - Non-recovery type divider - Google Patents

Abstract

PURPOSE:To execute division by the same algorithm even when a dividend is negative by providing the divider with a register capable of setting/resetting one bit. CONSTITUTION:The divider is constituted of an n-bit register(SRH) 1, an m-bit register(SRL) 2, an n-bit register(DR) 3, an adder/subtractor 4, and the register 5 capable of setting/resetting one bit. The register 5 is set up when the operated result of each line is '0' to discriminate that a partial residual is '0' and is reset when '1' is inputted to the least significant bit of each line of a dividend and a quotient is corrected by using the result of the register 5. Since the register capable of setting/resetting one bit is provided, division can be executed by the same algorithm even when a dividend is negative.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a non-recovery divider that can perform signed division at high speed by providing a register that can set and reset one bit. .

Conventional technology FIG. 2 is a block diagram of a conventional non-recovery divider.

In Figure 2, 1 is an n-bit register (SRH)
, 2 is the m-bit register (SRL), 3 is the n-bit register (DR), and 4 is the DR to the 5RHI.
This is an adder/subtractor that adds or subtracts 3.

Non-recovery division does not require addition for recovery, but instead the operation in each row is divided into addition and subtraction depending on whether the sign of the adder/subtractor output in the previous row matches the sign of the dividend. It needs to change. In other words, when the sign of the partial remainder becomes opposite to the dividend due to a failure in subtraction, it is necessary to generate "0" as the quotient and at the same time add the divisor in the next line. Also, if the sign of the partial remainder is not reversed, the quotient must be set to 1 and subtraction must be performed in the next line.

Table 1 shows an example of calculation.

Table 1 Example: Dividend S = (0,101001)2=(41/64)
10 divisor D=(0,111)2=(7/8)+.

TC: Two's complement, SF4: Partial remainder.

Sign bit ↓ Dividend S 0.101001 negative 0:)S
Shift R1, 110001<OQO=O5R
Add 1.10001DI 0.111 Positive (7) SR0,01101>OQl = Shift ISit Decrease 0.1101DR 1 1
．． OQl Negative SR1, 1111<OQ2=O Shift SR 1. l1l Add OR 0.111 Positive (7) SR0,110>OQ3=1 Quotient Q =QO,QIQ2Q3 =(Q, 101)t
=(5/8)t.

Remainder R=<0.00r3r4rsrs)z=(0,0
00110)2=(6/64)+.

Recoverable division Non-recoverable division 1st cycle 10 + D (recovery) 10th cycle - D/2 + D/2 Essential operation - D/2 D/2 Shift the divisor to the right when the trial operation fails After - getting results. In other words, in recovery binary division, after recovering the partial remainder by adding again, the divisor is shifted to the right (as in the divisor) to obtain the same result as subtraction. Table 2 shows this correspondence.

That is, the operation of division of unsigned binary numbers in FIG. 2 is as follows. Initially, "0" is assigned to 5RHI, a positive dividend S is assigned to 5RL2, and a positive divisor S is assigned to DR3. Next, 5RHI and 5RL2 are shifted to the left by 1 bit, and then DR3 is subtracted from SRH1, and the result is returned to 5RHI. Further, if the partial remainder at that time, that is, the output of the adder/subtractor is negative, "0" is assigned as a failure of subtraction, otherwise "1°" is assigned to the least significant bit of 5RL2.

Next, 5RHI and 5RL2 are shifted to the left by 1 bit, addition and subtraction are performed based on the previous addition and subtraction results, and the results are returned to SR and H1. Also, depending on the sign of the partial remainder, “
1” or “0” is assigned to the least significant bit of 5RL2.

Then repeat this a total of times.

Then, the quotient remains in 5RL2 and the remainder remains in 5RHI. However, since the remainder may be negative, if it is negative, it is assumed that the last subtraction has failed and the remainder must be recovered, that is, the divisor must be added.

Problems to be Solved by the Invention However, the conventional configuration described above cannot handle positive numbers, and in the case of a negative number, it is first corrected to positive before calculation is performed, and after the calculation, the quotient and remainder are changed to negative again if necessary. It had the disadvantage that it required an operation to return it.

The present invention solves the above conventional problems, and provides a non-recovery divider that can perform division using the same algorithm even when the dividend is negative by providing a register that can set and reset one bit. It is intended to.

Means for Solving the Problem In order to achieve this object, the non-recovery divider of the present invention calculates whether the operation result in each row is "0" in order to determine that the partial remainder is "0'°". It has a 1-bit register that is set when "1" is entered in the least significant bit of each row of the dividend, and is reset when "1" is entered in the least significant bit in each row of the dividend, and the result of this register is used to correct the quotient and remainder.

Effect With this configuration, even when the dividend or divisor is negative, it is possible to easily correct the quotient remainder, so division can be performed without replacing the dividend or divisor with a positive number. can.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a non-recovery type divider in one embodiment of the present invention, in which 1 to 4 are the same as in the conventional example, and 5
If the result of addition/subtraction is “O”, output (ZFLG
) becomes “1” and 5RHI.

When shifting 5RL2, “1” is placed in the least significant bit of 5RHI.
This is a register in which ZFLG becomes "O" when input.

Division of signed numbers in two's complement representation is realized by extending the algorithm for unsigned numbers in the conventional example.

First, the correspondence between positive and negative divisors is handled by reversing addition and subtraction. That is, in the case of subtraction, a method is used here in which all bits are inverted and "l" is added as a carry.

If the dividend is positive, the exact same algorithm as in the conventional example is used, and m additions and subtractions and one remainder correction are performed. If the value is negative, the addition and subtraction processes are reversed. In other words, in the same way that when the dividend is positive, the decision is made by subtracting and determining whether it exceeds "0" or not, when the dividend is negative, the decision is made whether or not it exceeds "0" by adding. judge. What should be noted here is the case of "O". Since “0” is a positive number in two’s complement representation,
This is not realized in the same way as when the dividend is positive, and it is necessary to detect and correct "O".

Figure 3 shows the 8-bit dividend (11011010)2-(
-38)+o is the 4-bit divisor (1101)2=(-3
)+o is shown as a calculation flowchart. The dividend is stored in SRL2 (m=8) and 5RHI (n=5
), 5RL2 is sign-extended and (11111)2 is entered. The divisor is sign extended (11101) and contains 2.

First, a left shift is performed and (11111)2 is entered into 5RHI. At this time, the least significant bit is “
Since it is 1, it is set to 2 and G is reset. Next, a subtraction is performed with the initial q being O”. Here, the result of the subtraction is (00101)2, so ZFLG is retained. Next, a left shift is performed again, and 5RHII
:(01011) 2 is entered. At this time, since the least significant bit is "1" as described above, ZFLG is reset. However, the value is the same as if it had not actually changed.

Next, since qo is "1", addition is performed. Here, the result of addition is (00010)2, so it is set to Z and G is retained. Below, the same process is repeated and finally the quotient (111
10011)2 and remainder (0001)2. Table 3 shows the addition/subtraction correspondence and the correction of the quotient and remainder.

(Margin below) The quotient is from Table 3 above, where the dividend is negative, the divisor is negative, and ZFL
Since G is "O", it is only necessary to invert the bits. Also,
For the remainder, just find the remainder + divisor. Then, the quotient (0000
1100)2=12, remainder (0001)2+(1101)
We get 2=(1110)2=-2. This is (-38
)÷(-3)=12...It matches the answer to (-2).

Now, regarding the logic shown in Table 3, each control signal is simple.

The initial q signal may be obtained by inverting the sign bit of the dividend. For addition/subtraction, the sign bit of the divisor + q signal may be used. ZFLG is as described above, and the sign bit of the remainder can be used to determine whether the remainder is positive or negative.

Note that when the dividend is "0" and the quotient remainder is calculated using the above procedure, it is conceivable that ZFLG is never set or reset and the value remains at the initial value. In this case, the quotient remainder is correct whether the initial value is set or reset, but by setting the initial value of ZFLG to "1", the dividend is negative when correcting the remainder, and ZFLG-
When “1”, the correction of substituting “O゛” into the remainder can be performed even when the dividend is positive, so the circuit can be reduced.Also, in order to avoid leaving uncertain signals in simulation etc. , the burden when considering circuits can be reduced.

Effects of the Invention According to the present invention, by providing a 1-bit register that can be set and reset, when the dividend or divisor is negative, the process of replacing it with the number of -counterpressure and performing division is omitted. It is possible to realize an excellent non-recovery type divider that can calculate the quotient remainder at high speed and using a constant algorithm that does not depend on the sign.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a non-recovery divider according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional non-recovery divider, and FIG. 3 is a flow chart of 8-bit to 4-bit calculation. 1... n-bit register (SRH), 2...
...m-bit register (SRL), 3...
- n-bit register (DR), 4...adder/subtractor, 5...1-bit set/reset register (ZFLG).

Claims (2)

[Claims] (1) In the non-recovery type division means, the operation result in each row is “0”.
”, and has a register that is reset when “1” enters the least significant bit in each row of the dividend, and the result of this register is used to correct the quotient and remainder. A non-recovery divider. (2) The non-recovery type divider according to claim (1), wherein the initial value of the register is set to a set state.