JPH03176735A - Multiplication remainder computing element - Google Patents

Abstract

PURPOSE:To prevent a circuit size from being expanded and to simplify the constitution of a circuit by repeating operation for storing an accumulated value obtained from an adder in a bidirectional shift register and finding out a remainder making positive values other than the multiplied value of two positive value as a module. CONSTITUTION:In the case of finding out the remainder to be positive value N other than multiplied value A.B of two positive values A, B as a module, a shift register 101 stores the value A, each bit from the least significant digit of respective digits of a binary expression is supplied at every bit to a bidirectional shift register 106 through a switch 105. Simultaneously, operation for storing accumulated values from the adder 103 in a register 106 is repeated to obtain the multiplied value A.B. Then operation for storing the outputs of the adder 103 in the register 106 is repeated at every supply of the inverted output of an inverter 104 to the register 106 through the switch 105. Consequently, the remainder to be N of the multiplier A.B as the module is obtained in the register 106.

Description

Detailed Description of the Invention (Technical Field to which the Invention Pertains) The present invention relates to a method for solving the problem of a product of two positive numbers (A, B) modulo another positive number N. remainder, (A-B
),. 6N) (hereinafter, this operation will be referred to as a remainder multiplication operation).

(Prior Art and Its Disadvantages) The above-mentioned multiplication remainder calculation unit is used for element calculations in coding/decoding processing in coding theory and cryptography theory.

In the conventional method of realizing such a modular multiplication unit,
Of the two positive numbers A and B used for multiplication, if the binary value representation of A is defined by the following formula (2 is the number of bits in the binary value representation of A), then the multiplication remainder value of A and B is (A-B). □ focuses on the following formula, and the calculation is roughly performed according to the following processing procedure.

Procedure ■ Store B in the shift register, and each time you shift 1 bit to the left (double operation), N is decreased only if the result is greater than the positive number N of the modulus. 24・B1. . . Calculate sequentially.

Procedure ■ When ai-“1”, for the past cumulative value, ■
(2'-B), obtained in . , N is newly accumulated and +(2'-B). .

seek.

Procedure ■ Only when the result obtained in step (■) above is greater than the modulus positive number N, subtract N to obtain the cumulative value.

By executing the above processes from ■ to ■ twice in order from the lowest via (LSB = ao) on the binary value representation of the positive number A to the highest bit (MSB = az-+) ,(A-B),. . can be found. FIG. 2 shows an example of the configuration of a conventional multiplication remainder calculator that executes these procedures.

In the figure, 201 is an auxiliary register that stores the above [2''・B), .4.4, and 202 is an adder that shifts the output of the auxiliary register 201 by 1 bit to the left, and
The auxiliary register A value obtained by subtracting N from the double value of the output value of 201 is output.

203 is a switch, which uses the MSB of the output of the adder 202 to change the value twice the output of the above 201 when the output of 202 is negative (MSB' = "1"), or to change the value to be positive (MSB - "0").
), the outputs of the adder 202, which are obtained by subtracting N from the double value, are respectively switched and input to the auxiliary register 201.

204 performs the above procedure ■ according to each digit ai of the binary value of A.
205 and 206 are adders, and 205 adds the output value of the accumulation value register 204 and the output value of the auxiliary register 201, and then goes to step (3). Outputs the new cumulative value shown.

On the other hand, like the adder 202, 206 uses the output of 205 as one input and the 2's complement value (-N) of the modulus positive number N as the other input, thereby eliminating N from the output value of 205. Output the value. 207 is a switch similar to 203, and when the output of 206 is negative (MSB=°゛bi°), the output value of the adder 205 is changed depending on the MSB of the output of the adder 206; When the value is “0”), the adder 205
The outputs of 206 with N removed from the outputs of are respectively switched and input to the cumulative value register 204. In addition, 20
4 inputs ai for each loop operation of 205, 207, and 204, and stores the output of 207 only when ai="1".

In the above configuration, the block 20B surrounded by the dashed line in FIG. When repeating a row, the cumulative value register 204
is the multiplication remainder value (A-B). 4N will be stored.

The above is an example of a configuration based on a conventional method.However, in such a configuration, there are three adders, two switchers, each of the same size, an auxiliary register, and an accumulated value. One register is required for each, which has the drawback of increasing the circuit scale.

(Object of the Invention) An object of the present invention is to alleviate the problem of circuit scale expansion that occurs in the conventional method, and to provide a relatively small-scale multiplication remainder arithmetic unit with a simple configuration.

(Structure and operation of the invention) [Structure precepts] FIG. 1 is a diagram showing a configuration example of an embodiment of the present invention.

101 is a shift register which stores one positive number A to be multiplied, and sets the number of significant digits in the binary representation of A to f(
l is a natural number), each digit ai in the binary value representation of A above (i=o~f-1) (7) Least significant digit (LSB)
from ao (i=o) to the most significant digit (MSB) at-
1 bits are sequentially outputted up to + (i=j! l) according to the clock signal CLK.

102 is a bus switch, which inputs the other positive number B to be multiplied and the two's complement value (-N) of the modulus positive number N, and switches according to the switching control signal R/L given from the outside. Switch output.

103 uses the output of the bus switch 102 as one input,
This is an adder that performs an addition operation with the other input and outputs the result.

104 is an inverter, and the MS of the output of the adder 103 is
B is input, inversion logic processing is performed, and MSB is output.

105 has the output ai of the shift register 101 as one input, the output MSB of the inverter 4 as the other input, and receives either of them as a switching control signal R/
This is a switch that outputs a switching parallel write signal PL to the outside according to the switching parallel write signal PL.

106 is a bidirectional shift register, which inputs the output of the adder 103 as parallel input data PI according to the clock signal CLK, and receives the parallel write signal P from the switch 105.
By L, parallel input data PI is temporarily stored when PL is "'1", parallel input data PI is discarded when PL is "0", data already stored is retained, and the data is stored at the time mentioned above. The stored data is shifted by one bit in the direction (left or right) specified by the switching control signal R/L according to the timing of the clock signal CLK, and is supplied to the adder 103 as parallel output data PO.

Its scale is (f+m) bits, where the number of significant digits in the binary representation of B is m (m is a natural number). The contents of this bidirectional shift register 106 can be initialized by a clear signal CLR applied from the outside.

[For production]

The operation based on the configuration example diagram of the present invention shown in FIG. 1 will be explained next.

First, the case where the switching control signal R/L is 'R'' (right) will be described.

The bus switch 102 has the content of the switching control signal R/L "R".
The circuit is switched according to the other positive number B that is subjected to multiplication.
is output and given to the adder 103. The adder 103 uses the output of the bidirectional shift register 106 as one input, and the output of the bus switch 102 as the other input, and performs an addition operation.
Output the result. The bidirectional shift register 106 takes in the output of the adder 103 according to the clock signal CLK, and receives the output from the adder 103 according to the parallel write signal PL.
When L is °1', the past cumulative value stored in the bidirectional shift register 16 is updated to the output value of the adder 103, and when L is °'0, no update is performed.

Further, the output of the switch 105 indicates that the switching control signal R/L is
In the case of "R", a shift is performed that stores one positive number A to be used for multiplication and sequentially outputs from the least significant digit a0 to the most significant digit alfi-+ in the binary value representation of A according to the clock signal CLK. The output of register 101 is connected and given to the bidirectional shift register as parallel write signal PL.

Through the above processing, (ao · 2° · B) is calculated the first time, and from the second time, one input of the adder 103 becomes the value obtained by shifting the value stored in the bidirectional shift register 106 by 1 bit to the right. Therefore, the output of the adder 103 is equivalent to adding twice the value of B to the value stored in the bidirectional shift register 106, and by repeating the above operation once, the switching signal R/L becomes In the case of L'' (left), the bus switch 102 switches and outputs the two's complement value (-N) of the modulus positive number N, and provides it to the adder 103.

The adder 103 uses the output of the bidirectional shift register 106 as one input and the output of the bus switch 102 as the other input, thereby outputting a value obtained by subtracting N from the output of the bidirectional shift register 106.

The output of the adder 103 is input to the bidirectional shift register 106 according to the clock signal CLK, and its M
SB is input to inverter 104.

The inverter 104 performs inversion logic processing, outputs MS and supplies it to the switch 105. The switch 105 switches and outputs the MSB as a parallel write signal PL in accordance with the switching control signal R/L, and supplies it to the bidirectional shift register 106. The output of the adder 103 is input to the bidirectional shift register 106 according to the clock signal CLK, and when the parallel write signal PL is "1" (the output of the adder 103 is a positive value), the value stored in the bidirectional shift register 106 is is updated to the output value of the adder 103, and the parallel write signal PL is “0” (adder 1
When the output of 03 is a negative value), the above update is not performed.
The next output of the bidirectional shift register 106 is shifted one bit to the left, and the most significant bit is discarded and output, and becomes a new input to the adder 103.

The above is 2”-N for AXB (k is any natural number)
It can be seen that this is nothing more than repeating the subtraction by eliminating k by 1, and a division process is executed in which AXB stored in the bidirectional shift register 106 is used as the dividend and a positive value N is used as the divisor.

Therefore, the remainder (AXB) obtained when the above process is repeated (l+m-n+1) times. □ will be left at the output of the bidirectional shift register 106.

(n is the number of significant digits of the two's complement value of N) (Effects of the Invention) As explained in detail above, according to the present invention, there are two switchers, two memories, and one adder. Since it can be realized, there is a remarkable effect that the circuit scale is relatively small.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration example of a conventional multiplication remainder calculator. 101... Shift register, 102... Bus switch, 103... Adder, 104... Inverter, 10
5... Switcher, 106... Bidirectional shift register,
201... Auxiliary register, 202, 205° 206.
...Adder, 203, 207...Switcher, 204...
- Accumulated value register, 208, 209... calculation block.

Claims (1)

[Claims] In calculating the remainder of the multiplication value A and B of two positive numbers A and B modulo another positive number N, the validity of the binary value representation of the positive numbers A, B, and N is determined. Number of digits l, m
, n (l, m, n are natural numbers), store the l-bit A, and write each digit a_i (i=0
~l-1) from the least significant digit a_0 to the most significant digit a_l_-_1 in accordance with an externally applied clock signal; A bus switch that inputs a 2's complement value of a positive number N and switches and outputs it according to a switching control signal given from the outside; and a bus switch that takes the output of the bus switch as one input and outputs the added value of the other input. an inverter that inputs the most significant digit a_l_-_1 of the output of the adder, performs inversion logic processing, and outputs it as an inverted output; a switch that switches and outputs according to a switching control signal; and a switch that inputs the output of the adder and the output of the switch according to a clock signal given from the outside, and that inputs the output of the adder according to the polarity of the output of the switch. In addition to controlling whether or not to store the output of the adder, a value obtained by shifting the stored value by one bit in the direction (left or right) specified by the switching control signal according to the timing of the clock signal is transferred to the other of the adder. It is equipped with a bidirectional shift register that can be output as an input and can arbitrarily initialize the stored value by a clear signal given from the outside. The bidirectional shift is performed by repeating l times the operation of storing the accumulated value obtained from the adder in the bidirectional shift register each time one bit is supplied from the switch to the bidirectional shift register. The multiplication values A and B are obtained in the register, and each time the inverted output of the inverter is supplied bit by bit from the switch to the bidirectional shift register, the accumulated value obtained from the adder is calculated. The operation to be stored in the bidirectional shift register is (l+m
-n+1) times to obtain the remainder modulo N of the multiplication values A and B in the bidirectional shift register.