JPS6349932A - Divider - Google Patents

Abstract

PURPOSE:To simultaneously drive respective dividers and to shorten dividing time by allowing a multiplication convergent type divider to execute normal division and allowing a non-recovery type divider 1 to execute division divided within a short period. CONSTITUTION:When a division start specification S is sent together with a divident M and a divisor N, a division control circuit 30 receiving the specification stores the divident M and the divisor N in a divident register 10 and a divisor register 11 in the non-recovery type divider 1 and a divident register 20 and a divisor register 21 in the multiplication convergent type divider 2 and then starts the operation of the dividers. The register 1 calculates the size of the divident M and the divisor N by a subtractor 12 and checks the plus or minus of the subtracted result in accordance with the polarity. On the other hand, the divider 2 forms multiplication for allowing the divisor N to approximate to '1' from the divisor N by a multiplier forming circuit 24 and stores the formed multiplier in a multiplier register 22.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a high speed division device.

[Conventional technology]

Conventionally, it was used as a divider for performing division processing.

Subtract the divisor from the dividend or partial dividend, and if the subtraction result is positive, set the quotient of that digit as "1", move the partial remainder by digit and use it as the partial dividend, and if the subtraction result is negative, set the quotient of that digit as "1". The most basic recovery type divider is known that calculates the quotient by repeating the operation of adding the divisor to 0'', adding the divisor again, and returning to the original value.In this divider, n-bit division requires n subtractions. The number of bits whose quotient is 0'' is added.

Also, as a high-speed 2-recovery divider.

Check the sign of the partial remainder, and if it is positive, set the quotient to ``1''.

The next digit operation subtracts the divisor, and if it is negative, the quotient is O
”, and the calculation of the first order digit is 2 by adding the divisor.
A non-restorative divider that omits the restorative addition is known.

On the other hand, unlike the aforementioned divider that repeats addition, subtraction, and shifting, by considering division as a fraction and selecting a number sequence in which the divisor of the 2 denominator approaches 1", and repeating multiplication on the dividend of the numerator, the numerator A multiplication convergence type divider is also known, which performs division by bringing the quotient closer to the quotient.

[Problem that the invention seeks to solve]

Among the conventional dividers mentioned above, in the case of recovery type dividers and non-recovery type dividers that repeat addition, subtraction and shifting, when the multiplicand cannot be divided into the last five digits, the number of bits at least equal to the bit length of the multiplicand is Although the two-circuit configuration is simpler than other dividers because it requires addition and subtraction of , it has the disadvantage that it takes a lot of processing time. On the other hand, a multiplicative convergence divider that calculates the quotient by repeating 1 multiplication is fast and
The larger the multiplier, the shorter the processing time. However, in the case of this divider, the quotient is found by approximation, so
2 because the processing time is determined regardless of the dividend and divisor values.
Recoverable and non-recovery dividers have the disadvantage that easily divisible divisions, which take less processing time than other divisions, take the same amount of processing time as other divisions.

[Failure to solve the problem]

The division device of the present invention subtracts the divisor from a positive partial dividend, adds the divisor to a negative partial dividend, and shifts the digits of the partial remainder obtained by the addition/subtraction. A non-recovery type divider that repeatedly calculates the dividend and the quotient of its digits is determined by the sign of the result of the addition/subtraction, and can omit the addition of 2 recovery; A number sequence in which the divisor of the denominator approaches ``1'', considering division as a fraction. A multiplication convergence type divider that performs division to obtain a quotient by selecting a divisor and a dividend and repeating multiplication on the divisor and dividend; When the partial remainder of the recovery type divider disappears.

If the multiplication convergence type divider stops the division process and the non-recovery type divider's quotient is used as the division quotient, and if the multiplication convergence type divider finishes the division as it is, then the non-recovery type divider and means for stopping the division process and using the quotient of the multiplication convergence type divider as the quotient of the division.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

In FIG. 1, reference numeral 1 surrounded by a dashed line indicates a non-recovery type divider, and 2 represents a multiplication convergence type divider.

Reference numeral 10 inside the non-recovery divider 1 is a dividend register that holds the dividend M or a partial dividend.

11 is a divisor register that holds the divisor N, and 12 is an output 100 of the dividend register 10 and an output 10 of the divisor register 11.
An adder/subtractor that performs addition and subtraction between 1 and 1.

13 is a remainder register that holds the output 102 of the adder/subtractor 12; 14 is a digit shift circuit that shifts the digits of the output 102 of the adder/subtractor 12; 15 is a code signal 1 of the operation result of the adder/subtractor 12;
The code Zosta holds 08.

105 is the output signal of the sign register 15, 16 is a quotient register that generates and holds a quotient from the sign signal 108 of the operation result of the adder/subtractor 12, and 17 is an all-zero detector that detects whether the output 103 of the remainder register 13 is all zeros. circuit,
107 is an output signal of the all zero detection circuit 17.

On the other hand, reference numeral 20 inside the squaring convergence type divider 2 denotes a dividend register 21 that holds the dividend M or an approximate value of the quotient.
is a divisor register that holds the divisor N or an approximate value of "1", and 22 is the quotient of the dividend M. A multiplier register that holds a multiplier for approximating the divisor to "1"; 23 is the output 200 of the dividend register 20 and the output 20 of the divisor register 21;
1 and the output 202 of the multiplier register 22; 24 is the output 201 of the divisor register 21;
Or the output 201 of the divisor register and the multiplier register 22
2o4 is the output of the multiplier generation circuit 24, which generates a multiplier from the output signal 203 of the multiplication result with the output 202 of .

Reference numeral 30 is a division control circuit that performs various division controls, S is an instruction to start division from a higher-level device, E is a division completion report to a higher-level device, 40 is a quotient output circuit, and Q is an output circuit 40
This is the quotient output from .

When a division start instruction S is sent from the host device along with a dividend M and a divisor N, the division control circuit 30 that received the instruction performs a squaring convergence type calculation with the dividend register 10 and divisor register 11 inside the non-recovery type divider 1. Dividend register 2 inside divider 2
0 and the divisor register 21 to hold the dividend M and the divisor N, respectively, and then the operation of each divider is started.

Inside the non-recovery divider 1, the dividend register 10 is first
In order to know the size of the dividend M held in the register 11 and the divisor N held in the divisor register 11, subtraction is performed by the adder/subtractor 12, and the sign signal 108 is used to confirm the sign of the subtraction result. When the subtraction result is positive, the dividend M is greater than the divisor N, so the highest order of the quotient register 16 is set to 1''.
If the value is negative, the divisor N cannot be subtracted because it is larger than the dividend M, so the highest order of the quotient register 16 is set to "O". At the same time, the partial remainder on the output 102 of the adder/subtractor 12 is shifted to the left by one digit in the digit shift circuit 14 and then stored in the dividend register 10 as a new partial dividend. The code signal 108 of the adder/subtractor 12 is also stored in the code register 15. Note that the quotient register 16 is cleared to zero at the start of the division process.

Then, we move on to calculating the quotient of the second digit. The sign register 15 holds the sign of the partial remainder of the previous digit, and when this sign is positive, the partial remainder up to the previous time is valid, so subtraction is performed.
When the value is negative, addition is performed between the partial dividend held in the dividend register 10 and the divisor M held in the divisor register 11 using the adder/subtractor 12. Then, the quotient of the corresponding digit to be stored in the quotient register 16 is calculated from the sign of the new partial remainder.

Then, in order to calculate the quotient of the next digit, the partial dividend created by shifting the new partial remainder and its sign are stored in the dividend register 1o and the sign register 15, respectively.

Repeat until. Note that the output 103 of the remainder register 13 is constantly checked by the all-zero detection circuit 17, and when all zeros are stored in the remainder register 13, when the dividend M is evenly divisible by the divisor N, all zeros from the all-zero detection circuit 17 are output. The division control circuit 30 receives the detection signal 107.

The output circuit 40 uses the output 106 of the quotient register 16 as the quotient Q.
The control signal 300 is used to output the output from the control signal 300, and the earth is removed.

On the other hand, inside the squaring convergence type divider 2, a multiplier for approximating the divisor N to 1'' is first created from the divisor N held in the divisor register 21 in the multiplier creation circuit 24, and then stored in the squaring number register 22. .

Then, the dividend M held in the dividend register 20
After the multiplier 23 multiplies the approximation multiplier held in the multiplier register 22, the dividend approximated to the quotient is stored in the dividend register 2o.

Next, the first approximation divisor obtained by multiplying the divisor N held in the divisor register 21 and the first approximation multiplier held in the multiplier register 22 by the multiplier 23 is sent to the multiplier generation circuit 24. Here, a second approximation multiplier is created and stored in the multiplier register 22. At this time, the output 203 of the multiplier 23
The first approximate divisor above is stored in the divisor register 21.

This operation is repeated until a termination instruction is received from the division control circuit. The division control circuit 30 outputs the output 20 of the divisor register 21.
1", the division process is stopped when the output 201 becomes 1", and the approximation value of the quotient held in the dividend register 20 is set as the quotient Q and the control signal 300 is used from the output circuit 40. The division completion report E is transmitted to the host device.Then, the operations of the non-recovery type divider 1 and the multiplication convergence type divider 2 are stopped.

In general, a non-recovery divider uses n
Addition and subtraction are performed, but if it is divisible in the middle of the division, the partial quotient at that stage becomes the official quotient.

In addition, in the case of a squaring convergence type divider, the quotient is an approximation of the dividend to the quotient when the divisor reaches 1'', so the processing time is faster than that of a non-recovery type divider. The value does not affect the length of processing time.Also, the processing time required to approximate the divisor is almost the same, so when using a square convergence type divider, the processing time does not depend on the data.Therefore, it is easy to divide. For division, a non-recovery divider takes less time to process.9For normal division, the quotient is calculated by a multiplication convergence divider, but for division that is easily divisible, a non-recovery divider is used. Especially, you can calculate the quotient quickly.

〔Effect of the invention〕

As explained above, in the present invention, the non-recovery type divider and the multiplication convergence type divider are operated simultaneously, the squaring convergence type divider is responsible for normal division, and the non-recovery type divider is responsible for division that can be divided in a short time. By taking charge of each divider, you can take advantage of the features of each divider.

This has the effect that the optimum divider suitable for each division data can be adopted, and the division processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a division device according to an embodiment of the present invention. 1...Non-recovery type divider, 2...Multiplication convergence type divider. 10.20... Dividend register, 11, 21... Divisor register, 12... Addition/subtractor, 13... Remainder register. 14... Digit shift circuit, 15... Sign register, 16
... Quotient register, 17... All zero detection circuit, 2
2... Multiplier register, 23... Multiplier, 24...
Multiplier creation circuit, 30... Division control circuit, 40... Output circuit.

Claims (1)

[Claims] 1. In a division device that calculates a quotient from a dividend and a divisor,
Repeatedly subtracting the divisor from the dividend or positive partial dividend, adding the divisor to the negative partial dividend, and shifting the digits of the partial remainder obtained by the addition and subtraction to obtain the partial dividend. , the quotient of the digit is determined by the sign of the addition/subtraction result, and the non-recovery type divider can omit the recovery addition;
a multiplication convergence type divider that performs division to obtain a quotient by selecting a sequence of numbers approaching `` and repeating multiplication on the divisor and dividend; monitoring the presence or absence of a partial remainder of the non-recovery type divider;
If the partial remainder of the non-recovery type divider disappears during division, stopping the division process of the multiplication convergence type divider,
The quotient of the non-recovery type divider is used as the quotient of division, and if the multiplication convergence type divider finishes the division as it is, the division process of the non-recovery type divider is stopped, and the multiplication convergence type divider and means for determining the quotient of the division as the quotient of the division.