SU682894A1 - Arithmetical apparatus - Google Patents

Description

The division and multiplication buses are connected, and the algebraic addition bus is connected to the second input of the first element AND. The third input of the first element I is connected to the output of the first element OR, and the output to the first inputs of the fourth, fifth, sixth and seventh elements I. The output of the second operand counter is connected to the input of the second operand zero decoder, the first input of the eighth element I is connected to the output of the decoder the zero of the first operand, the output of the eighth element AND with the input of the counter of the first operand, the output of the decoder the zero of the first operand with the first input of the first element OR, with the third input of the third element AND, with the input of the first element NO, with the first The input of the ninth element I. The output of the zero-decoder of the second operand is associated with the first input of the tenth element AND, the input of the second element NOT, the second input of the first element OR, the third input of the second element And, and the fourth input of the third element I. Output the trigger sign of the first operand is connected to the first input of the unequal element and with the second input of the ninth element AND, the output of the trigger of the sign of the second operand with the second input of the unequality element and with the second input of the tenth element And, the output of the unequal element - with the input of the third element NOT, with the second input of the sixth element AND and with the second input of the fourth element AND, the output of which is connected to the nepiBOMy input of the second element OR. The output of the first element is NOT connected to the first input of the eleventh AND element, to the first input of the third OR element, to the third input of the tenth And element, to the first input of the twelfth And element, and to the third input of the sixth AND element connected by its output to the first input of the fourth element OR. The output of the second element is NOT connected to the third input of the ninth AND element and the second input of the third OR element connected to the second input of the fifth element I. The output of the third element is NOT connected to the third inputs of the fifth and seventh AND elements, as well as to the first inputs thirteenth and fourteenth elements I. The output of the second element AND is connected to the first input of the fifth element OR, and to the second input of the fourth element OR, the third and fourth inputs of which are connected: to the outputs of the seventh and twelfth elements AND, respectively but. The output of the first element AND is connected to the second input of the fifth OR element connected by its output to the second input of the eighth AND element, the output of the third AND element - to the third input of the fifth OR element and to the second input of the second OR element, the third and fourth inputs of which are connected to the outputs of the fifth and eleventh elements And, respectively, and the output to the input of the result counter. The outputs of the ninth, tenth, thirteenth, and fourteenth elements And are connected to the inputs

the sixth OR element, the output of which is connected to the trigger input of the result sign. The output of the fourth element OR is connected to the input of the counter of the second operand, the algebraic addition bus, with four inputs of the ninth and tenth elements, AND, the multiplication bus, with the second inputs of the twelfth and fourteenth elements, AND, and the division bus, with the second inputs of the eleventh and thirteenth elements. AND.

The drawing shows a structural diagram of an arithmetic unit.

The device contains in its composition

generator / imluses, subtracting counter 2 of the first operand, trigger 3 characters of the first operand, subtracting counter 4 of the second operand, trigger 5 characters of the second operand, summing result counter 6 and trigger 7 characters of the result. The device also includes the decoders 8 and 9 zero of the first and second operands, respectively, the element 10 inequality, the elements And //, 12 and 13, designed

for blocking the generator / impulses at the end of the operadium, respectively, for algebraic addition, division and multiplication, the elements I / 4 and 15, which provide for algebraic addition, input

pulses of the count to the input of counter 6, respectively, when the characters of the operands coincide and do not match, the element OR 16, through which the counting impulses pass to the input of the counter 2, the element I 17, which provides

the formation of the private module in the division, the element OR 18, through which the counting pulses are fed to the input of the counter

6, element 19, by which the information unit is subtracted from the multiplier module, placed in counter 4 at multiplication, elements 20 and 21, which provide for algebraic addition the input of counting pulses to the input of counter 4, respectively, if the signs of the components match or do not match, the element OR 22, through which the counting pulses arrive at the counting input of counter 4, the elements OR 23 and 24, which control the counting under algebraic addition, the elements AND

25-28, intended to form a sign of the result, an OR element 29 translating the sign of the result into a trigger

7, the elements are NOT 30, 31 and 32, the element And 33, blocking the counting input of the counter 2. K

The inputs of the device are connected to the bus 34 of algebraic sloseni, the bus 35 division and the bus 36 multiplication.

Consider the operation of the device when performing algebraic addition, multiplication, and division.

Algebraic operation implementation.

First, consider the case, t-svogda term signs do not cope. In this case, it is necessary to take into account that in the algebraic addition of two numbers with different signs, the modulus of the sum is equal to the difference of the modules of the terms, and the sign of the sum coincides with the sign of the term with a large module. This provision is implemented in the described arithmetic unit as follows.

Let iB counters 2 and 4 be written in the forward code terms with mismatched signs, and counter 6 be reduced to the zero state. Then, at the outputs of the descorers 8 to 9, a resolving voltage level is formed, and at the output of the inequality element 10, for the forbidden level. The resolution level from the output of the decoder 8 is fed to the elements And 55 and 25, as well as the element OR 23 vi to the input of the element NOT 30. The resolution level from the output of the decoder 9 is fed to the elements AND 2U and 26, as well as to the element OR 23 and to the input element HE 31. The inhibiting level from the output of the inequality element 10 is fed to the elements AND 74 and 20, as well as to the input of the element NOT 52. At the same time, the output of the element OR 24 (thanks to the elements NOT 30 vi 31) forms a inhibitory level, which is fed to the input of the element 15, to another input of which from the output of the element is NOT 52 t resolving level. From the output of the element NOT 52, the permitting level is also fed to the input of the element AND 21. The inhibiting level from the output of the element NO 30 is supplied to the elements 20 and 26, and the prohibiting level from the output of the element NOT 31 is also fed to the element 25. elements 25 and 26 are submitted to the level of stress from the unit outputs of the triggers 5 and 5, respectively.

The resolution level, taken from the output of the element OR 23, is fed to the input of the element AND 11, which, when the algebraic addition field 34 is excited, is unlocked, providing the flow of counting pulses to the inputs of the elements 14 and .15 locked by the levels of voltages removed from the outputs element 10 inequality and element OR 24, respectively. The counting pulses also go to the locked element AND 20 and to the open element And 2 / and, moreover, through the element OR / b to the open element And 35. From the output of the overlapped element And 55, the counting pulses go to the counting input of counter 2, and from the output an open element AND 21 through the element OR 22 - to the counting input of the counter 4. This thereby ensures the synchronous subtraction of "units from the modules of both components.

As soon as the counter, IR of one of the terms is reset (at this point, the difference of the modules of the terms will be formed in the counter of the other term), the counting input by its prohibiting level, removed from the output of the corresponding decoder zero, is blocked, the output of one of the elements HE 30 and 31 is formed allowing the level that is transmitted through the element OR 24 to the input of the element AND 15. The latter is unlocked, and the counting pulses through the element OR 18 begin to flow into the counting input of counter 6 until the counter also resets the other agaemogo. Then, at both inputs of the element OR 25, the voltage levels become prohibiting, the output level of the voltage level is also set at its output, as a result of which the element 11 stops counting. In counter 6, the difference of the modules of the terms.

The sign of the algebraic sum is formed as follows.

When counting, the scorer 2 is zeroed first, then at the output of the decoder 8, the level of pressure becomes forbidding, and at the output of the element is NOT 30 allowing. This level is fed to the input of the AND element 26, at one of the inputs of which there is already a permitting level from the output of the decoder 9 (since counter 4 has not yet been reset). The input element And 26 is supplied by the algebraic addition field 34 that is excited at that time, as well as by the single output of the trigger 5. If trigger 5 is in the zero state (the addend with a large module is positive) element AND 26 does not work and trigger 7 does not change its initial (zero) state, which ensures that the sign of the algebraic sum matches the sign of the term with a large module. If trigger 5 is set to one (the addendum with a large modulus is negative), AND 26 through the OR element 29 translates a high level from the single output of this trigger to the input of trigger 7, which due to this also moves to a single state, and the algebraic sign the amount is negative. Upon subsequent zeroing of the counter 4, the sign of the zeroed earlier term (i.e., the information recorded in trigger 5) is not rewritten into trigger 7, TaiK k; K element 25, when the counter 2 is reset, is blocked by prohibiting voltage removed from the output of decider 8 .

In the case of an earlier zeroing of counter 4, the resolving voltage level taken from the output of the element NOT 3 through the elements AND 25 and OR 29 rewrites the information on the sign of the term written in trigger 7, and again, the sign of the algebraic sum of the component with

large module. For1The interdiction level from the output of the decoder 9 (supplied to the element And 26), while blocking the flow of information regarding the sign of the addendum with the smaller module to the trigger 7.

Consider the case when the signs of the terms coincide. It should be noted that. in the case of an algebraic addition of two points with the same signs, the sum modulo module is the sum of the modules of the terms, and the sign coincides with the characters of the terms. This position in the device is realizable. by successive translation first module, recorded -. the counter 2, then the module recorded in the counter 4, into the counter 6. The character of the sum sign is performed in the same way as in the case of a mismatch between the signs of the terms. Naturally, in this case, by virtue of the sequence in zeroing counting of count 2, and 4, the sign of the algebraic sum coincides with the sign of the term written in trigger 3 of the term written in trigger 5.

When writing numbers with matching characters respectively in counters 2 and 4 levels and nationalities at the outputs of the elements of the device; the properties are set such as JI. In the described case, the inconsistencies of the signs of the items, except for the levels of eg Kenyards at the output of the W element of unequal ambiguity and, as a result, at the output of the HE 32, which are reversed. By virtue of this, elements 15 and 21 are blocked for the entire counting time. Element AND 14 is unlocked, and Element 20 is prepared for unlocking by resetting the counter. The resolving voltage level from the output of the OR 23 element when the algebraic arc bus 34 is excited unlocks the AND 11 element, and the counting pulses go through the unlocked AND 14 element to the OR 18 element at the counting input of counter 6 and through the OR 16 element at the counting input of counter 2. resetting counter 2 in counter 6 yields the modulus of the first addend. In this case, a high level of voltage, taken from the output of the element NOT 30, unlocks the element I 20 and begins the addition of the content of account iika 4 (module of the second term) with those already entered into the counter 6 by the model of the first term. When counter 4 is also zeroed, the prohibiting voltage level is set at the output of the OR 23 s, which, when applied to the input of the AND // element, stops counting.

So, having written down in advance counters 2 and 4, the direct codes of the terms, with any possible combination of modules and signs (The latter have the opportunity, having excited the algebraic addition bus 34, to get a direct CODE of algebraic sum. We have the corresponding sign.

The implementation of the multiplication operation.

Operators of multiplication in the proposed arithmetic unit realize the correspondence with the equality

BUT . B + B +. . + B,

And the terms,

Following this, the product module can be obtained by adding one module of one Hs multiplier with itself as many times as there are units in the module of another factor. With this product a positive sign is attributed if the signs of the factors coincide and a negative sign otherwise.

The noted positions are implemented in the arithmetic unit described as follows.

After recording in the forward code, the somnol-ives, respectively, in the counter 2 and 4, at the outputs of the decipherors 8 to 9, the resolving voltage level is set (unless the modules of the somno.residents are not equal to zero). The interlocking voltage level from the output of the decryptor. Is applied to the input of the elements I, 1.3, 33, as well as to the input of the element NOT 30, from the output of which the inhibiting voltage level passes to the input of the element 13. 13. The allowable voltage level from the output of the decoder 9 enters another INPUT of the element 13. When the bus 36 is multiplied, the counting pulses from the generator output / through the unlocked AND element 13 are fed to the inputs of the OR 16 and 18. From the output of the OR 16 element through the unlocked AND 33, the counting pulses go to counting input counting counter 2, and from the output of the ILR1 18 element, the counting pulses go to the counting input of the summing counter 6. This ensures the transfer of the multiplier factor recorded in the meter 2 to the counter 6. As soon as the counter 2 is zeroed, it restores to the next count pulse. the direct code corresponding to the value of the module recorded by iB counter 2. The process of zeroing the counter 2 and then restoring the module code of the corresponding co-multiplier in it causes a command at the output of the element NOT 30 positive voltage pulse, th through the unlocked element AND 19 (the multiplication bus 36 is excited) and through the element OR 22 enters the counting input of the subtracting counter 4 and reduces the content of the latter by one. In a manner that, after each resetting, the restoration of counter 2, the contents of counter 6 are increased by an amount equal to the value of the module modulus recorded in counter 2, and the contents of counter 4 are reduced by one. The counting continues until the counter 4 is zeroed out. As soon as the counter 4 is zeroed, the output of the decoder 9 is formed

the prohibiting level valr nenia which being fed to the input of the element And 13 blocks the flow of counting pulses into the device. In counter 6, a modulus of the numbers written in counters 2 and 4 is obtained.

If any of the factors is zero, the prohibiting voltage level is formed at the output of the corresponding decoder (8 or 5). When applied to the input element And 13 blocks the flow of counting pulses into the device, the counter 6 remains in its original (zero) state this ensures the equality of the bullet module of the product.

The product symbol is formed by element 10 of the ambiguity, element 32, element 32 and element 27, and element 29. If the signs of factors multiply at the output of element 32, a inhibitory level is obtained, as a result of which the inhibit level and trigger 7 the bullet state changes, thereby assigning a positive sign to the product. If there is a discrepancy between the characters at the factors at the output of the HE 32 element, a resolving voltage level is obtained, which through the unlocked AND 27 element (the multiplication bus 36 connected to the second input of the And 27 element is excited) and through the OR element 29 enters the trigger input 7 and transfers it in a single state, a negative sign is attributed to the product. So, having previously recorded counters 2 and, accordingly, the direct codes of factors with any signs, it is possible to excite the multiplication bus 36 and restore it in the process ETA in the counter 2 (as it zeroing) .kod corresponding modulo factors recorded in the counter, to receive the product of the forward code with the appropriate sign.

Implement the dividing operation.

In the proposed arithmetic unit, the division division is implemented in accordance with the following obvious position:

A: In N, then it can be argued that the expression

 - B -... - B

N subtractions

is zero with excess. Moreover, if A is a multiple of B, there is a strict equality.

It follows from the above that the modulus of the quotient of two numbers with the corresponding accuracy can be obtained by determining how many times the divider module can be subtracted from the divisible module. This is attributed to the particular (as with multiplication, the positive sign when the signs of the operand coincide, and negative otherwise).

Marked in the described arithmetical device is implemented as follows.

Divisible; in the forward code, it is written into counters 4, the divisor is counted into counters 2, the counter, 6 is brought to its initial (zero) state. In this case, the resolution level of the voltage from the output of the decimator 8 is fed to the outputs of the element NO 30 and the element AND 33, unlocking.: I am the last, but authorizing

the voltage level from the output of the decipheror 9 (unless the dividend is not equal to zero) passes to the input of the element 12, the inhibiting level of the voltage from the output of the element NOT 30 enters the input of the element

And / 7. With vozb; During the dividing bus 35, counting pulses from the generator output / through the open element 12 are fed to the inputs of the elements OR 16 and 2 {2. From the output of the element OR, 16 through the unlocked element

And 33 counting pulses are fed to the counting input of the subtractive counter 2, and from the output of the element OR 22 - to the counting input of the subtractive counter 4. This thereby ensures the synchronous subtraction of units from the modules and the dividend and the divisor. As soon as counter 2 is zeroed, the direct code is restored in it to the next counting pulse, corresponding to the value of the divider module.

The process of zeroing the counter 2 with the subsequent restoration of the direct code corresponding to the value of the divider module is accompanied by the appearance at the output of the element HE 30 positive

voltage pulse, which through the unlocked element I / 7 (the division bus is excited) and through the element OR 18 enters the counting input of summing counter 6 and increases the content of the latter (equal to initially zero) by one. Thus, after each zeroing - (recovering counter 2, the contents of counter 4 are reduced, by the value of the divider module, and the contents of counter 6 are incremented. The count continues until counter 4 is reset. As soon as counter 4 is zeroed, the output decoder 9 is formed prohibitive voltage level, which being

served on the input element And 12 overlaps the flow of pulses into the device. In counter 6, a private module is obtained.

If the dividend recorded in the counter 4 is zero, then at the output of the decoder 9 a suppressing voltage level is formed, which being fed to the input element And 12 blocks the flow of counting pulses into the device, meanwhile the counter 6 remains in the original (zero 11

BOM) state, and this ensures that the modulus of the quotient is zero.

The sign of the private division is formed in the same way as it is done in multiplication, only "the position of the element AND 27, and so on, the element AND 28 takes part.

Thus, dividing the dividend and divisor with any characters in the direct code, respectively, in counter 2, and by triggering the dividing bus 35, it is possible to restore the code in divider in counter 2 (as it zeroes) the code corresponding to the divider module, Get direct (approximate) private code with corresponding signs.

The accuracy of the calculations during the execution of the division can be increased. To do this, place the module of the dividend, in counter 4, not the first digit of the counter, but from a certain rth bit. Then the last r-1 bits of the modulus of the quotient obtained in counter 6, with the corresponding accuracy, represent the fractional part of the quotient.

Compared with the prototype in the considered arithmetic unit, it uses one counting register less, due to which the wins in the obo, ore. In addition, in contrast to the prototype, both the operands and the result of the operation involve only the IB direct code, which eliminates the need to transform the codes of the operands.

The advantage of the descriptive device in comparison with the traditional arithmetic unit built on three registers (one of which is accumulating) is a significant reduction in the amount of hardware used for one bit. This is achieved by eliminating the chains by shifting and reducing the amount of equipment in the chips transfers. In addition, unlike the traditional arithmetic unit, it does not require prior transformation of the operand codes.

Claims (3)

Invention Formula An arithmetic unit containing a pulse generator, elements And, a result counter, a counter of the first and second operands, a decoder zero. The first operand, the output of the pulse generator connected to the first input of the first element And, the output of the counter of the first operand zero connected to the input of the zero decoder The first operand, characterized in that, in order to reduce the amount of hardware used, the device additionally contains the elements OR, NOT, the element of equivalence, the triggers of the sign in the operands and the result, decrypted zero second operand, wherein the generator output is connected with the first impulsav vho12 The second and third elements AND, the second inputs of which are connected to the dividing and multiplying bus, the second input of the first AND element are connected to the algebraic addition bus, the third input of the first AND element is connected to the output of the first OR element, and the output is from the first .in the inputs of the fourth, the t, and the seventh elements And, the output of the counter The second operand is connected to the input of the zero decoder of the second operand, the first input of the eighth element is And is connected to the output of the zero decoder of the first operand, (OUTPUT of the eighth element And is connected to the input of the counter of the first operand, the output of the zero decoder. The first operand of the first operand. is connected to the first input of the first element OR, to the third input of the third element AND, to the input of the first element NOT and to the first input of the ninth element AND, the output of the neutral zero of the second operand . is connected with the first (INPUT of the tenth element AND, with the input of the second element NOT, with the second input of the first element OR, with the third the input of the second element And with the fourth input of the third element And, the output of the trigger, the sign of the first operand is connected to the first input of the element. equals and the second input of the fourth element And, VYHOD D trigger sign of the second operand is connected to the second input of the unequal element and with the second input of the tenth element And, the output of the unequal element is connected to the input of the third element NOT, with the second input of the sixth element AND, and with the second input of the fourth element AND, the output of which is connected to the first input of the second element OR, the output of the first ele ment | is NOT connected to the first input of the eleventh AND element, to the first input of the third element OR, to the third input the tenth element And, with the first input of the twelfth element And, and with the third input of the sixth element And, connected by its the outputs to the first input of the fourth element OR, the output of the second element is NOT connected to the third input of the ninth element AND with the second input of the third element OR connected by the output to the second input H of that element AND the output of the third element is NOT connected to the third inputs of the fifth and the seventh elements And, as well as to the first inputs of the thirteenth and fourteenth elements And, the output of the second element AND is connected to the first input of the fifth OR element and to the second input of the fourth OR element, the third and fourth inputs of which are connected to the outputs of the seventh and twelfth elements AND, respectively, the output of the first AND element is connected to the second input of the OR element whose output is connected to the second input of the eighth element And, the output of the third element And is connected to the third input The fifth element OR .i with the second input of the second element OR, the third and fourth inputs of which are connected to the outputs of the fifth and eleventh elements AND, respectively, and the OUTPUT - 1K to the input of the result counter, the outputs of the ninth, tenth, thirteenth and fourteenth elements And are connected with the inputs of the sixth element OR, the output of which is connected to the input of the result sign trigger, the output of the fourth element OR is connected to the input of the counter of the second operand, the algebraic addition bus is connected to the fourth pass of the ninth and tenth elements ntov And multiplying bus connected to the second inputs of the twelfth and fourteenth element and dividing the tire is connected to the second inputs of the eleventh and thirteenth elements I. Sources of information received note in the examination: 1.Avtorskoe № Certificate USSR 392495, cl. G 06 F 7/39, 1971. 2. USSR author's certificate number 394785, cl. G 06 F 7/50, 1971. 3. Authors certificate of the USSR (No 368599, class G 06 F 7/38, 1969 (prototype).