JPH0619703B2 - Divider - Google Patents

Description

TECHNICAL FIELD The present invention relates to a high speed division device.

[Conventional technology]

Conventionally, as a divider for performing division processing, a divisor is subtracted from a dividend or a partial dividend, and if the subtraction result is positive, the quotient of that digit is set to "1", the partial remainder is moved to a partial dividend, and Also, when the subtraction result is negative, the most basic recovery type divider is known in which the quotient of the digit is set to "0", the divisor is added again, and the operation of returning the original is repeated to obtain the quotient. In this divider, in n-bit division, n times of subtraction and addition of the number of bits whose quotient is "0" are performed.

In addition, as a speed-up of the recovery type divider, the sign of the partial remainder is checked, and if it is positive, the quotient is set to "1". For the calculation of the next digit, the divisor is subtracted. 0 ",
There is known a non-recovery type divider that omits addition for recovery by adding a divisor for the operation of the next digit.

On the other hand, unlike the above-mentioned divider that repeats addition and subtraction and shift, by considering division as a fraction, selecting a sequence in which the divisor of the denominator approaches "1", and repeating multiplication in the numerator dividend as well. There is also known a multiplication / convergence type divider that performs division by bringing the numerator closer to the quotient.

[Problems to be solved by the invention]

Among the conventional dividers described above, in the case of recovery-type dividers that repeat addition and subtraction and shift and non-recovery-type dividers, when the last digit of the multiplicand is not divisible, at least the same number of additions and subtractions as the bit length of the multiplicand Since it is necessary, the circuit configuration is simpler than other dividers, but it has the drawback of requiring a long processing time. On the other hand, a multiplication-convergence divider that finds a quotient by repeating multiplication can find the quotient by several multiplications if a dedicated multiplier is used. Becomes shorter. However,
In the case of this divider, since the quotient is obtained by approximation, the processing time is determined regardless of the values of the dividend and divisor, so the recovery-type and non-recovery-type dividers have a shorter processing time than other divisions. The division that is divisible by has the disadvantage that it takes the same processing time as other divisions.

[Means for solving problems]

The division apparatus of the present invention subtracts a divisor from a dividend or a partial dividend, adds a divisor again when the subtraction result becomes negative, and returns it to the original value. When the subtraction result becomes positive, the digit of the partial remainder obtained is obtained. It is repeated by moving and setting it as a partial dividend, and the quotient of that digit is determined by whether or not subtraction was successful. A recovery type divider that performs division with the same principle as the method of writing; consider division as a fraction. , A multiplication-convergence type divider that performs division to obtain a quotient by selecting a sequence in which the denominator divisor approaches “1” and repeating multiplication with respect to the divisor and dividend; When the partial remainder of the recovery-type divider is monitored during the division, the division processing of the multiplication-convergence-type divider is stopped, the quotient of the recovery-type divider is used as the division quotient, and the multiplication is performed. The convergent divider ends the division as it is. When the division processing of the recovery-type divider is stopped, and a means for the quotient of dividing the quotient of the multiplication convergent divider.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

In FIG. 1, reference numeral 1 surrounded by a one-dot chain line is a recovery type divider, and 2 is a multiplication convergence type divider.

Reference numeral 10 inside the recovery type divider 1 is a dividend register holding a dividend M or a partial dividend, 11 is a divisor register holding a divisor N, and 12 is an output 100 of the dividend register 10 and an output 101 of the divisor register 11 is subtracted. A subtracter, 13 is a remainder register that holds the output 102 of the subtractor 12, 14 is a digit shift circuit that shifts the digits of the output 102 of the subtractor, and 15 is the output 103 of the remainder register 13 and the output 101 of the divisor register 11. An adder 105, an output signal of the adder 15, a quotient register 16 for making and holding a quotient from the polarity of the subtraction result of the subtractor 12, and a reference numeral 17 for detecting whether or not the output 103 of the remainder register 13 is all zero. All zero detection circuit, 107 is all zero detection circuit 17
Is the output signal of.

On the other hand, the reference numeral 20 in the multiplication / convergence type divider 2 indicates the dividend M
Alternatively, the dividend register that holds the approximate value of the quotient, 21 is the divisor register that holds the approximate value of the divisor N or "1",
22 is a multiplier register that holds a multiplier for approximating the dividend M and the divisor to "1", and 23 is either output 200 of the dividend register 20 or output 201 of the divisor register 21 and output 202 of the multiplier register 22. A multiplier for multiplying with, 24 is the output 201 of the divisor register 21 or the output 201 of the divisor register 21
And output signal 203 of the multiplication result of the output 202 of the multiplier register 22
A multiplier creating circuit for creating a multiplier from and, 204 is an output of the multiplier creating circuit 24.

Further, reference numeral 30 is a division control circuit for performing various control of division,
S is a division start instruction from the host device, E is a division end report to the host device, 40 is an output circuit of the quotient, and Q is a quotient output from the output circuit 40.

When the division start instruction S is sent from the host device together with the dividend M and the divisor N, the division control circuit 30 which has received the instruction causes the dividend register 10 and the divisor register 11 inside the recovery type divider 1.
Then, the dividend register 20 and the divisor register 21 inside the multiplication / convergence type divider 2 are controlled to hold the dividend M and the divisor N respectively, and then the operation of each divider is started.

In the recovery type divider 1, the magnitude of the dividend M held in the dividend register 10 and the divisor N held in the divisor register 11 is first calculated by the subtractor 12 and the polarity signal 10
Confirm the sign of the subtraction result with 8. When the result of the subtraction is positive, it means that the divisor N has been subtracted from the dividend M. Therefore, the uppermost digit of the quotient register 16 is set to "1" and the partial remainder on the output 102 of the subtractor 12 is moved to the digit shift circuit. After shifting 1 digit to the left by 14, the dividend register 10 is added as a new partial remainder.
To store. If the subtraction result is negative, the divisor N cannot be subtracted larger than the dividend M, so the quotient register
The top of 16 is set to "0" and the output of subtractor 12 is 10
Output 101 of divisor register 11 to remainder register 13 holding 2
Is added by an adder 15 to return it to the original dividend M, and the digit shift circuit 14 shifts it to the left to store a partial dividend twice the dividend M obtained in the dividend register 10. Note that the quotient register 16
Is cleared to zero at the start of divisor processing.

Next, the subtractor 13 subtracts the partial dividend newly held in the dividend register 10 by the subtractor 13, and in the same manner, the quotient of the next digit to be stored in the quotient register 16 is obtained from the polarity of the new partial remainder.

This operation is repeated until an end instruction is received from the division control circuit 30. The output 103 of the remainder register 13 is constantly checked by the all-zero detection circuit 17, and the remainder register 13
When all zeros are stored in, that is, the dividend M is the divisor N
When the division control circuit 30 receives the all-zero detection signal 17 from the all-zero detection circuit 17, the division control circuit 30 receives the output 106 of the quotient register 16 as the quotient Q and outputs the control signal 300 from the output circuit 40.
To output the division end report E to the host device. Then, the operations of the recovery type divider 1 and the multiplication convergence type divider 2 are stopped.

On the other hand, inside the multiplication / convergence type divider 2, first, a multiplier for approximating the divisor N to “1” from the divisor N held in the divisor register 21 is created by the multiplier creating circuit 24 and then stored in the multiplier register 22. To do.

Then, the multiplier M held in the dividend register 20 and the approximation multiplier held in the multiplier register 22 are multiplied by each other.
After multiplication by 23, the dividend approximated to the quotient is the dividend register 20
Stored in.

Next, the multiplier N held in the divisor register 21 and the first approximation multiplier held in the multiplier register 22 are multiplied by each other.
The first approximation divisor obtained by multiplying by 23 is input to the multiplier creating circuit 24, where the second approximation multiplier is created and the multiplier register 22
To store. At this time, the first approximate divisor on the output 203 of the multiplier 23 is stored in the divisor register 21.

This operation is repeated until an end instruction is received from the division control circuit 30. The division control circuit 30 monitors the output 201 of the divisor register 21, stops the division process when the output 201 becomes "1", and at this time, outputs the approximate value of the quotient held in the dividend register 20 as the quotient Q. Then, the output circuit 40 outputs it by using the control signal 300, and the division end report E is transmitted to the host device. Then, the operations of the recovery type divider 1 and the multiplication convergence type divider 2 are stopped.

In general, a recovery-type divider performs n times of subtraction on an n-bit division and adds the number of bits for which the quotient is “0”. However, if the division is completed during the division, the partial quotient at that stage is Become a formal quotient.

In addition, in the case of a multiplication-convergence type divider, the quotient is a quotient of the dividend when the divisor becomes “1”, so the processing time is faster than that of the recovery-type divider, but the value of the dividend is Does not affect the processing time. Further, since the processing time required for the approximation of the divisor is almost the same, the processing time does not depend on the data when the multiplication / convergence type divider is used. For this reason, since the processing time is shorter in the recovery-type divider for easily divisible division, the quotient is calculated by the multiplication-convergence-type divider in the case of normal division, but in the case of easily divisible division, the recovery-type divider is used. The quotient can be calculated quickly by using.

〔The invention's effect〕

As described above, according to the present invention, the recovery-type divider and the multiplication-convergence-type divider are simultaneously operated, the multiplication-convergence-type divider is responsible for normal division, and the restoration-type divider is responsible for division that can be divided in a short time. As a result, the advantages of each divider can be utilized, the optimum divider that suits each division data can be adopted, and the division processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a divider according to an embodiment of the present invention. 1 ... Recovery type divider, 2 ... Multiplying convergence type divider, 10,20
…… Dividend register, 11,21 …… Divisor register, 12 ……
Subtractor, 13 ... Remainder register, 14 ... Digit shift circuit, 15 ...
… Adder, 16 …… quote register, 17 …… all-zero detection circuit, 22 …… multiplier register, 23 …… multiplier, 24 …… multiplier creation circuit, 30 …… division control circuit, 40 …… output circuit.

Claims (1)

[Claims] 1. A division device for obtaining a quotient from a dividend and a divisor, subtracting a divisor from a dividend or partial dividend, adding a divisor again when the subtraction result becomes negative, and returning the subtraction result to a positive result. Then, the obtained partial remainder is moved to the next digit and the partial dividend is repeated, and the quotient of the digit is determined by whether or not the subtraction was successful. The recovery method is the same as the method of writing. A divider and a multiplication-convergence-type divider that considers division as a fraction, selects a sequence in which the denominator divisor approaches "1", and repeats multiplication on the divisor and dividend to perform division to obtain a quotient; The presence / absence of a partial remainder of the type divider is monitored, and when the partial remainder of the recovery type divider is exhausted during the division, the division processing of the multiplication / convergence type divider is stopped and the quotient of the restoration type divider is stopped. Is the quotient of division, and Serial When the multiplication convergent divider is directly terminates the division, the recovery-type divider of division processing is stopped, the divider device having a means for the quotient of dividing the quotient of the multiplication convergent divider.